SoylentNews is people
SoylentNews
Today, we've decided to revisit some of the worst CPUs ever built. To make it on to this list, a CPU needed to be fundamentally broken, as opposed to simply being poorly positioned or slower than expected. The annals of history are already stuffed with mediocre products that didn't quite meet expectations but weren't truly bad.
Note: Plenty of people will bring up the Pentium FDIV bug here, but the reason we didn't include it is simple: Despite being an enormous marketing failure for Intel and a huge expense, the actual bug was tiny. It impacted no one who wasn't already doing scientific computing and the scale and scope of the problem in technical terms was never estimated to be much of anything. The incident is recalled today more for the disastrous way Intel handled it than for any overarching problem in the Pentium micro-architecture.
We also include a few dishonourable mentions. These chips may not be the worst of the worst, but they ran into serious problems or failed to address key market segments. With that, here's our list of the worst CPUs ever made.
- Intel Itanium
- Intel Pentium 4 (Prescott)
- AMD Bulldozer
- Cyrix 6×86
- Cyrix MediaGX
- Texas Instruments TMS9900
Which CPUs make up your list of Worst CPUs Ever Made?
(Score: 2) by shortscreen on Friday April 24 2020, @06:41AM
Speaking of CPUs that are bad... not just underpowered or overhyped or badly marketed, but bad. The Atari Jaguar CPUs deserve a mention.
The Jag designers tried to roll their own CPU. Aaand I'm sorry but they failed. It's comparable to other RISC CPUs of the time except that it's badly broken. A lot of instructions will create a register conflict with adjacent instructions. Some of these cause a pipeline stall. Other ones do NOT cause a stall, they just result in data corruption. Dummy instructions have to be inserted here and there to deliberately cause a stall to get correct results. There were one or two registers that were part of the general purpose register file which would always get trashed by an interrupt so you couldn't use them if you were using interrupts.
The Jag had two of these in total, one each embedded into the Tom and Jerry chips, with 4KB and 8KB of internal RAM respectively. But it wasn't cache RAM, it was directly addressable. And code had to run from there, because even though they could access the 64-bit main memory bus (32 bits at a time) there was a bug which caused branch instructions to be unreliable if executed from main memory. (Years later, some clown on a forum who claimed to have a workaround for this filed a software patent on it...)