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posted by martyb on Thursday April 23 2020, @12:33PM   Printer-friendly
from the Sorry-about-that-boss! dept.

Worst CPUs:

Today, we've decided to revisit some of the worst CPUs ever built. To make it on to this list, a CPU needed to be fundamentally broken, as opposed to simply being poorly positioned or slower than expected. The annals of history are already stuffed with mediocre products that didn't quite meet expectations but weren't truly bad.

Note: Plenty of people will bring up the Pentium FDIV bug here, but the reason we didn't include it is simple: Despite being an enormous marketing failure for Intel and a huge expense, the actual bug was tiny. It impacted no one who wasn't already doing scientific computing and the scale and scope of the problem in technical terms was never estimated to be much of anything. The incident is recalled today more for the disastrous way Intel handled it than for any overarching problem in the Pentium micro-architecture.

We also include a few dishonourable mentions. These chips may not be the worst of the worst, but they ran into serious problems or failed to address key market segments. With that, here's our list of the worst CPUs ever made.

  1. Intel Itanium
  2. Intel Pentium 4 (Prescott)
  3. AMD Bulldozer
  4. Cyrix 6×86
  5. Cyrix MediaGX
  6. Texas Instruments TMS9900

Which CPUs make up your list of Worst CPUs Ever Made?


Original Submission

 
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  • (Score: 1, Interesting) by Anonymous Coward on Friday April 24 2020, @06:24PM

    by Anonymous Coward on Friday April 24 2020, @06:24PM (#986624)

    And the actual Cyrix stuff got sold to someone else, because the AMRISC/RDC 3286 (There were a couple different names for it depending on the mode) was a Cyrix 486SLC-133 which may or may not have been related to the 6x86 cores, which I will note were Speculative execution 2+ years before Intel put out the Pentium Pro. In fact the biggest issue with the 6x86 was because they were microcoded speculative execution chips. A sequence of 2-3 instructions could actually put the chip in an infinite loop because it would mask interrupts. this sequence was possible in userspace which could cause an infinite loop if a workaround wasn't implemented. Apparently a page fault was enough so using a 2 page interrupt table was a method of mitigation.

    The bigger issue with the 6x86 was the lack of a timestamp counter and a few other items needed for full pentium compatibility, and the fact that the FPU in it was weaker than the Pentium FPU because they had focused the transistor budget on integer processing because at the time it seemed like general purpose cpus focused on integer use was where it was at. Unfortunately Pentium and Doom proved them wrong, followed shortly thereafter by the Pentium MMX leading to the merger of the PPro and the P55C's MMX extensions into the Celeron/P2/Xeon lines. And the rest as they say is history.

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