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TSMC Has Started The Development of The 2nm Lithography Process
Earlier this month, we saw that TSMC was getting its CoWoS interposer and 5nm production lines at full capacity. Yesterday, we found out that AMD and Nvidia bought up all of their excess capacity for next-generation GPU and CPU development. They have also been making advancements in 3nm process development, but have not been able to put much work in because many of the tools necessary are currently unavailable or hard to find due to the COVID-19 pandemic. 3nm is already a lot of work as it is, but in a recent shareholders meeting, DigiTimes was able to figure out that TSMC is already planning to start the development of the 2nm Lithographic process.
TSMC's "3nm" node has reportedly been delayed by 6 months due to the pandemic. Samsung is facing similar delays on their own "3nm" node.
TSMC's "5nm" production has not been delayed, and AMD will reportedly use an exclusive enhanced "5nm" node for Zen 4 CPUs in 2021.
Previously: TSMC's Chip-on-Wafer-on-Substrate (CoWoS) Connects Multiple Interposers
High Demand Reported for TSMC's Chip-on-Wafer-on-Substrate Packaging
(Score: 2) by bzipitidoo on Saturday April 25 2020, @08:35PM (3 children)
Yes, architecture matters a great deal. A 1990 CPU such as the 80486, scaled down to a 14nm node, will be vastly inferior to a 2020 CPU at 14nm, even if, for fairness, you limit the 2020 chip to one core. It's still 64bit vs 32bit, and the newer one has a ton of enhancements such as the MMX and SSE instructions, ability to talk to faster buses (PCIe vs ISA with, possibly, VESA Local Bus), a whole lot more cache, and all the pipelining, out-of-order execution, branch prediction, and, uh, yeah, speculative execution. What would the performance difference still be, if the 486 was put on an even footing? Perhaps 10x?
But as you say, marketing has rendered node size meaningless. Maybe a better measure would be average number of transistors per sq mm? I don't doubt that whatever measure anyone manages to invent, they'll find ways to game it.
More issues with the decade old boxes is that they can't use a 128G flash drive, the USB ports are only 2.0, the display interface is DVI (still okay for now), they don't have much RAM by today's standards, and who knows how much longer the aging hard drives will last? Oh yeah, they're also power hungry.
(Score: 2) by takyon on Saturday April 25 2020, @10:31PM (2 children)
Scaling down without doing anything to the design can get you decreased power consumption and maybe clock speed boosts. An example being game consoles like PS3 that got slim versions. The PS3 Cell processor went from 90 to 65 to 45nm, and the GPU went from 90 to 65 to 40 to 28nm.
For an i486, maybe you need to make some design changes to even accommodate multi-GHz clock speeds. And you could shrink the die size from 165 mm2 [cpu-world.com] (1.2 million transistors [jimdofree.com]) to... 0.01 mm2 or less.
Yes, transistors per mm2 is good info. The AnandTech article I linked says 96.27 million transistors per mm2 for TSMC "7nm", and 177.14 mTr/mm2 for TSMC "5nm", which is where the 84% improvement comes from. One benefit I forgot to mention is reduced latency from having denser and closer cores, SRAM, etc. You can also increase the amount of cache without impacting latency as much.
Raspberry Pi 4, although it has limitations, can smoke a lot of those 90s and early 2000s desktop systems. The single-board computers and slightly larger form factors stand to gain big if 3DSoC makes it out of the fab, since it could deliver HEDT performance at single digit wattage. If we accept that computer performance is already good enough for most users, then we will see power consumption cut by 90-99%, and then performance increased on top of that.
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(Score: 0) by Anonymous Coward on Saturday April 25 2020, @11:14PM (1 child)
Parent said:
"Scaling down without doing anything to the design can get you decreased power consumption..."
This was only a certainty for the 20th century. Past a certain size, parasitic (leakage) effects started to dominate. You could no longer "just shrink" the same lithography. Different transistor architectures such as FinFET, silicon on insulator, etc. had to be invented to mitigate the massive power waste that was occurring from shrunk, "old school" transistor designs. Now, with the new and improved transistor designs, do size shrinks tend to reduce power? Yes, but it's not a given it will automatically happen. At these small sizes, managing power leakage is a challenge.
(Score: 3, Informative) by takyon on Saturday April 25 2020, @11:45PM
Ok, so changes happen to transistor designs on the new nodes to make them work. FinFET, GAAFET, etc. TSMC has had a pretty good track record [anandtech.com] (see table) of each node reducing power consumption at the same clock speed. Looks like 87.2% reduction from "20SOC" to "5FF".
For the hypothetical of shrinking the 486, you would have to make changes to get it on "5nm" or "3nm".
AMD and many other chip designers are fabless. They can sign a contract with TSMC, Samsung, GlobalFoundries, or even Intel, and hopefully companies like SkyWater soon (monolithic 3D at larger nodes). If there weren't any improved nodes available, they would just sit on the same node but take advantage of improved yields and better binning, or make bigger changes to the architecture.
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