Stories
Slash Boxes
Comments

SoylentNews is people

posted by martyb on Wednesday June 17 2020, @04:31PM   Printer-friendly
from the falconry++ dept.

On July 7, AMD will launch three refreshed Zen 2 "Matisse" desktop CPUs with slightly higher boost clocks than the previous versions:

  • 12-core Ryzen 9 3900XT will boost to 4.7 GHz, instead of 4.6 GHz for the 3900X.
  • 8-core Ryzen 7 3800XT will boost to 4.7 GHz, instead of 4.5 GHz for the 3800X.
  • 6-core Ryzen 5 3600XT will boost to 4.5 GHz, instead of 4.4 GHz for the 3600X.

The 3900XT and 3800XT will not come with a bundled cooler, unlike the 3900X and 3800X (the top-of-the-line 16-core 3950X also did not come with a cooler). 3600XT will come with a Wraith Spire cooler.

The "suggested etailer price" (SEP) is the same as the launch prices for the previous CPUs ($499, $399, $249), but the 3900X is often sold for $400-$420 instead of $500, for example. So customers may end up paying between 10-25% more for a 2-5% potential performance gain, unless retailers drop the prices soon after launch.

The new 3000XT family of processors focuses mostly on boosting the turbo frequency by 100-200 MHz for the same power. AMD states that this is due to using an optimized 7nm manufacturing process. This is likely due to a minor BKM[*] or PDK[**] update that allows TSMC/AMD to tune the process for a better voltage/frequency curve and bin a single CPU slightly higher.

[...] In each [of the] three cases, the XT processors give slightly better frequency than the X units, so we should expect to see an official permanent price drop on the X processors in order to keep everything in line.

The CPUs should work with existing motherboards that supported the non-XT CPUs, after a BIOS update.

A September to October 2020 launch date is likely for the first next-generation Ryzen 4000 Zen 3 "Vermeer" CPUs. Rumors of the launch being pushed back to 2021 have been denied.

[*] BKM: Best-Known Method
[**] PDK: Process Design Kit


Original Submission

 
This discussion has been archived. No new comments can be posted.
Display Options Threshold/Breakthrough Mark All as Read Mark All as Unread
The Fine Print: The following comments are owned by whoever posted them. We are not responsible for them in any way.
  • (Score: 3, Informative) by takyon on Thursday June 18 2020, @06:45PM

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Thursday June 18 2020, @06:45PM (#1009652) Journal

    Get ready for DDR5 channel inflation:

    https://www.micron.com/-/media/client/global/documents/products/white-paper/ddr5_more_than_a_generational_update_wp.pdf [micron.com]

    In addition to higher data rates and improvements to the I/O circuitry, DDR5 introduces other new protocol features unrelated to data rate that are integral to increasing bandwidth and performance. For example, DDR5 DIMMs feature two 40-bit (32 bits plus ECC) independent channels. When combined with a new default burst length of 16 (BL16) in the DDR5 component, this allows a single burst to access 64B of data (the typical CPU cache line size) using only one of the independent channels, or only half of the DIMM. Providing this ability to interleave accesses from these two independent channels enables tremendous improvements to concurrency, essentially turning an 8-channel system as we know it today into a 16-channel system.

    --
    [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
    Starting Score:    1  point
    Moderation   +1  
       Informative=1, Total=1
    Extra 'Informative' Modifier   0  
    Karma-Bonus Modifier   +1  

    Total Score:   3