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Cerebras More than Doubles Core and Transistor Count with 2nd-Generation Wafer Scale Engine

posted by martyb on Wednesday August 19 2020, @01:36AM   Printer-friendly
from the Amdahl's-law? dept.

takyon writes:

342 Transistors for Every Person In the World: Cerebras 2nd Gen Wafer Scale Engine Teased

One of the highlights of Hot Chips from 2019 was the startup Cerebras showcasing its product – a large 'wafer-scale' AI chip that was literally the size of a wafer. The chip itself was rectangular, but it was cut from a single wafer, and contained 400,000 cores, 1.2 trillion transistors, 46225 mm2 of silicon, and was built on TSMC's 16 nm process.

[...] Obviously when doing wafer scale, you can't just add more die area, so the only way is to optimize die area per core and take advantage of smaller process nodes. That means for TSMC 7nm, there are now 850,000 cores and 2.6 trillion transistors. Cerebras has had to develop new technologies to deal with multi-reticle designs, but they succeeded with the first gen, and transferred the learnings to the new chip. We're expecting more details about this new product later this year.

Previously: Cerebras "Wafer Scale Engine" Has 1.2 Trillion Transistors, 400,000 Cores
Cerebras Systems' Wafer Scale Engine Deployed at Argonne National Labs

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  • (Score: 2) by takyon on Wednesday August 19 2020, @01:39AM (6 children)

    by takyon (881) <takyonNO@SPAMsoylentnews.org> on Wednesday August 19 2020, @01:39AM (#1038638) Journal

    https://www.cerebras.net/product/#explorer-3 [cerebras.net]

    The CS-1 is an internally water-cooled system. Like a giant gaming PC on steroids, the CS-1 uses water to cool the WSE, and then uses air to cool the water. Water circulates through a closed loop internal to the system.

    Two hot-swappable pumps on the top right move water through a manifold across the back of the WSE, cooling the wafer and warming the water. Warm water is then pumped into a heat exchanger. This heat exchanger presents a large surface area for the cold air blown in by the four hot-swappable fans at the bottom of the CS-1. The fans move air from the cold aisle, cool the warm water via the heat exchanger, and exhaust the warm air into the warm aisle.

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  • (Score: 2) by RS3 on Wednesday August 19 2020, @02:03AM (5 children)

    by RS3 (6367) on Wednesday August 19 2020, @02:03AM (#1038650)

    15 kW power consumption for 1, uh, "chip".

    • (Score: 3, Funny) by Rosco P. Coltrane on Wednesday August 19 2020, @02:06AM (1 child)

      by Rosco P. Coltrane (4757) on Wednesday August 19 2020, @02:06AM (#1038651)

      On the plus side, if a chip fails QC, it can always be sold as a space heater.

      • (Score: 2) by RS3 on Wednesday August 19 2020, @03:44AM

        by RS3 (6367) on Wednesday August 19 2020, @03:44AM (#1038693)

        I hope it's mounted horizontally. Regardless of the cooling system, at those power levels the silicon's liable to slump.

    • (Score: 4, Informative) by takyon on Wednesday August 19 2020, @02:08AM

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Wednesday August 19 2020, @02:08AM (#1038653) Journal

      Sometimes, to be energy efficient, you need to dump all the energy into one big ass chip. At least, according to Cerebras.

      They didn't give any wattage for the 2nd-generation chip, but maybe it will go down. The size should be around the same, and the TSMC "7nm" process node is substantially more efficient than "16nm".

      https://en.wikichip.org/wiki/7_nm_lithography_process#TSMC [wikichip.org]

      TSMC original 7-nanometer N7 process was introduced in April 2018. Compared to its own 16-nanometer technology, TSMC claims its 7 nm node provides around 35-40% speed improvement or 65% lower power. Compared to the half-node 10 nm node, N7 is said to provide ~20% speed improvement or ~40% power reduction. In terms of density, N7 is said to deliver 1.6x and 3.3x improvement compared to N10 and N16 respectively. N7 largely builds on all prior FinFET processes the company has had previously. To that end, this is a fourth-generation FinFET, fifth-generation HKMG, gate-last, dual gate oxide process.

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    • (Score: 2) by driverless on Wednesday August 19 2020, @02:58AM (1 child)

      by driverless (4770) on Wednesday August 19 2020, @02:58AM (#1038681)

      I was at the Hot Chips presentation when they introduced this... the response from industry professionals was a near-universal WTF, it just doesn't make sense to pile everything onto one monster device when you can avoid the near-insurmountable engineering problems just by going with many smaller ones. Even Cerebras admitted that every time someone's tried WSI it's failed, "but this time it's different". Surprised to see they're still around, presumably they're relying on a couple of near-infinite-budget national-lab customers to keep going.