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Fudzilla have 'obtained' a slide showing details of a forthcoming APU from AMD based on their new "Zen" architecture.
The highest end compute HSA part has up to 16 Zen x86 cores and supports 32 threads, or two threads per core. This is something we saw on Intel architectures for a while, and it seems to be working just fine. This will be the first exciting processor from the house of AMD in the server / HSA market in years, and in case AMD delivers it on time it might be a big break for the company.
Each Zen core gets 512 KB of L2 cache and each cluster or four Zen cores is sharing 8MB L3 cache. In case we are talking about a 16-core, 32-thread next generation Zen based x86 processor, the total amount of L2 cache gets to a whopping 8MB, backed by 32MB of L3 cache.
This new APU also comes with the Greenland Graphics and Multimedia Engine that comes with HBM memory on the side. The specs we saw indicate that there can be up to 16GB of HBM memory with 512GB/s speed packed on the interposer. This is definitely a lot of memory for an APU GPU, and it also comes with 1/2 rate double precision compute, enhanced ECC and RAS and HSA support.
The new APU sports quad-channel DDR4 support, with up to 256GB per channel at speeds of up to 3.2GHz. No information yet on which processor socket this APU will use, but it's safe to assume the DDR4 support alone will render it incompatible with all AMD's current motherboards. Support is also included for secure boot and AMD's encryption co-processor.
(Score: 4, Interesting) by LoRdTAW on Tuesday April 14 2015, @02:57PM
Some really interesting stuff here. My one question is whether the HBM (high bandwidth memory) is only for the GPU or is part of the main 64bit memory space and available to the OS. And is 512GB/s for the HBM speed or the interconnect fabric total bandwidth? If the former, it would be interesting to see what a machine with 16GB of main memory running at 512GB/s could do computationally wise with all those cores. Then you throw 4 channel DDR4 memory on top of that. I'd like to see how it stacks up to Intel's Iris Pro with eDRAM. I am hoping the memory hierarchy looks like this: L1->L2->L3->HBM->DDR4.
My next question is how does the HBM interface to the APU? Is it a separate memory controller in addition to the quad channel DDR4? Is it on a DIMM or soldered to the motherboard like a video card or game console? Would hate to see motherboards hamstrung with 2-4GB HBM that can't be upgraded without tossing the motherboard. In that case I'd go balls out and buy a 16GB board assuming it doesn't put me in the poor house.
And lastly, Nothing is mentioned about hypertransport USB3. So either this APU will never see multi socket use or AMD is abandoning multi socket NUMA systems and focousing on single package many core systems. Then again, multicore and clustering seems to be pushing it into obsolescence. Still, I wonder if the southbridge is a simple PCIe device or the APU is moving closer to an SoC on steroids (like the AMD G series SoC).
(Score: 1, Informative) by Anonymous Coward on Wednesday April 15 2015, @04:28AM
With AMD's HSA push, it would be very surprising if the HBM isn't in shared address space.