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posted by takyon on Thursday May 07 2015, @02:15AM   Printer-friendly
from the making-a-comeback dept.

Today was Advanced Micro Devices' (AMD) 2015 Financial Analyst Day. The last one was held in 2012. Since then, the company has changed leadership, put its APUs in the major consoles, and largely abandoned the high-end chip market to Intel. Now AMD says it is focusing on gaming, virtual reality, and datacenters. AMD has revealed details of upcoming CPUs and GPUs at the event:

Perhaps the biggest announcement relates to AMD's x86 Zen CPUs, coming in 2016. AMD is targeting a 40% increase in instructions-per-clock (IPC) with Zen cores. By contrast, Intel's Haswell (a "Tock") increased IPC by about 10-11%, and Broadwell (a "Tick") increased IPC by about 5-6%. AMD is also abandoning the maligned Bulldozer modules with Clustered Multithreading in favor of a Simultaneous Multithreading design, similar to Intel's Hyperthreading. Zen is a high priority for AMD to the extent that it is pushing back its ARM K12 chips to 2017. AMD is also shifting focus away from Project Skybridge, an "ambidextrous framework" that combined x86 and ARM cores in SoCs. Zen cores will target a wide range of designs from "top-to-bottom", including both sub-10W TDPs and up to 100W. The Zen architecture will be followed by Zen+ at some point.

On the GPU front, AMD's 2016 GPUs will use FinFETs. AMD plans to be the first vendor to use High Bandwidth Memory (HBM), a 3D/stacked memory standard that enables much higher bandwidth (hence the name) and saves power. NVIDIA also plans to use HBM in its Pascal GPUs slated for 2016. The HBM will be positioned around the processor, as the GPU's thermal output would make cooling the RAM difficult if it were on top. HBM is competing against the similar Hybrid Memory Cube (HMC) standard.

Although High Bandwidth Memory is on track for 2016, it will actually be featured in an AMD desktop GPU to be released this quarter. AnandTech expects HBM to become a standard feature in AMD APUs, which benefit from higher memory bandwidth:

Coupled with the fact that any new GPU from AMD should also include AMD's latest color compression technology, and the implication is that the effective increase in memory bandwidth should be quite large. For AMD, they see this as being one of the keys of delivering better 4K performance along with better VR performance.

Finally, while talking about HBM on GPUs, AMD is also strongly hinting that they intend to bring HBM to other products as well. Given their product portfolio, we consider this to be a pretty transparent hint that the company wants to build HBM-equipped APUs. AMD's APUs have traditionally struggled to reach peak performance due to their lack of memory bandwidth – 128-bit DDR3 only goes so far – so HBM would be a natural extension to APUs."

AMD's Carrizo APUs will be released beginning this quarter, but it may be worth it to wait:

Badging aside, AMD still will have to face the fact that they're launching a 28nm notebook APU versus Intel's 14nm notebook CPUs, the company is once again banking on their strong GPU performance to help drive sales. Coupled with the combination of low power optimizations in Carrizo and full fixed-function hardware decoding of HEVC, and AMD will be relying on Carrizo to carry them through to 2016 and Zen.

AMD also announced Radeon M300 discrete GPUs for notebooks, promising "refined efficiency and power management" as well as DirectX 12 support.

One of the more interesting chips on AMD's roadmap may be a "high-performance server APU" intended for both high-performance computing and workstations.

Alternate coverage at Tom's Hardware and The Register.

 
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  • (Score: 3, Informative) by takyon on Thursday May 07 2015, @05:13PM

    by takyon (881) <takyonNO@SPAMsoylentnews.org> on Thursday May 07 2015, @05:13PM (#179988) Journal

    Yes, yes, yes, and yes.

    They could actually be complementary.

    http://en.wikipedia.org/wiki/Hybrid_Memory_Cube [wikipedia.org]

    Hybrid Memory Cube (HMC) is a high-performance RAM interface for through-silicon vias (TSV)-based stacked DRAM memory competing with the incompatible rival interface High Bandwidth Memory (HBM).

    http://www.hybridmemorycube.org/faq.html [hybridmemorycube.org]

    At the foundation of HMC is a small logic layer which sits below vertical stacks of DRAM die connected by through-silicon via (TSV) bonds. An energy optimized DRAM array provides efficient access to memory bits via the logic layer, providing an intelligent memory device truly optimized for performance and energy efficiencies. This elemental change in how memory is built into a system is paramount. By placing intelligent memory on the same substrate as the processing unit, each part of the system can do what it's designed to do far more optimally than any previous technology.

    http://www.eetimes.com/document.asp?doc_id=1261415 [eetimes.com]

    Designers envision placing the Micron stack on a chip substrate next to a server or network processor to provide new levels of fast memory access for high performance systems. Micron says it will deliver early next year 2 and 4 Gbyte versions of the stack providing aggregate bi-directional bandwidth of up to 160 Gbytes/second.

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  • (Score: 2) by bob_super on Thursday May 07 2015, @05:38PM

    by bob_super (1357) on Thursday May 07 2015, @05:38PM (#179994)

    Designers envision taking off from my driveway and commuting to Mars too.

    As of today, HMC is a discrete chip, and not a small one at that. The chaining feature only works of you have physical space for multiple ones, and would be counter-productive on a on-substrate implementation.

    • (Score: 2) by takyon on Thursday May 07 2015, @05:42PM

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Thursday May 07 2015, @05:42PM (#179996) Journal

      If HBM can do it, I'm sure HMC can do it. The specification is already on version 2 and no products are out yet.

      I stand by my use of "competing" and "similar" to describe the relationship between HBM and HMC.

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