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posted by mrcoolbp on Tuesday May 12 2015, @06:00AM   Printer-friendly
from the factory-is-probably-already-compromised-by-NSA dept.

The Moscow Center for SPARC Technologies has released a quad-core chip built on a 65 nm process:

Despite the company's own name, the chip is actually built on the proprietary "Elbrus" instruction set architecture and not on SPARC. The CPU cores are clocked only at 800 MHz each, and the chip is manufactured on a rather old 65 nm process. The chip has a TDP of 45 W, which isn't too bad considering its target market [of high-performance PCs and servers].

However, the performance may be lacking. Going by the MCST's own benchmarks (shown above and below), the CPU is only compared with older Atom chips that used to target netbooks or (also old) "Pentium-M" notebook processors. Even if the Elbrus-4C wins by a large margin in the floating point score, it does so against obsolete processors. When it is compared against the others for integer performance, the difference is much smaller.

The Register speculates that this chip may be the first effort to wean Russia off of "compromised" Intel and AMD processors.

The Elbrus 4c used in the PCs and servers is said to support two instruction sets: very long instruction word and SPARC. It's also said to be capable of x86 emulation, and to run Linux natively, after one performs binary translation.

The Elbrus ARM-401 PC is a minitower packing a version of Linux also called Elbrus and boasts four USB 2.0 ports, a PCI-express slot, gigabit ethernet and not much more. The CPU is apparently capable of running Doom 3, enabling Russian gamers to go fragging like it's 2004.

The Server Elbrus 4.4 is a four-socket affair and four of the machines fit into a 1U chassis. Gigabit ethernet, SATA and plenty of PCI slots connect it to other kit and the rest of the worlds.

MCST has announced the products are on sale, but don't expect an online configurator at which you can run up a rig and get a live price: the outfit offers just the sales@mcst.ru email address for would-be buyers.

 
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  • (Score: 3, Insightful) by jmorris on Tuesday May 12 2015, @06:15AM

    by jmorris (4844) on Tuesday May 12 2015, @06:15AM (#181813)

    Not going to make jokes about the performance (or lack of) of this new chip. The miracle is always getting a new design built at all, making an existing design go faster always seems to be more a matter of throwing more money at the problem. The question I'd want to ask is why the heck they built in two instruction sets. Seems that needlessly complicates the design and for a first attempt there would need to be a sound reason for it. SPARC isn't exactly a terrible ISA, it is licensable and the patent situation should even be fairly clean by now. Meanwhile VLIW hasn't exactly set the world on fire although it does seem to get used internally it seems like vendors hide it to avoid the problem of supporting the same one across product lines. Wonder if this isn't exactly the same situation and something is lost in translation?

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  • (Score: 1, Informative) by Anonymous Coward on Tuesday May 12 2015, @06:33AM

    by Anonymous Coward on Tuesday May 12 2015, @06:33AM (#181821)

    (1) Nobody will use it or take it seriously if it isn't backward compatible with x86.
    (2) It's not a first attempt or even a new design; Elbrus dates back to 1973. [wikipedia.org]

  • (Score: 0) by Anonymous Coward on Tuesday May 12 2015, @07:03AM

    by Anonymous Coward on Tuesday May 12 2015, @07:03AM (#181833)

    The miracle is always getting a new design built at all, making an existing design go faster always seems to be more a matter of throwing more money at the problem.

    If that's the case they should license and use ARM stuff. That way it's not just them throwing money at the problem but others around the world.

  • (Score: 3, Informative) by TheRaven on Tuesday May 12 2015, @08:40AM

    by TheRaven (270) on Tuesday May 12 2015, @08:40AM (#181865) Journal

    The miracle is always getting a new design built at all, making an existing design go faster always seems to be more a matter of throwing more money at the problem

    Code reuse is still a very new concept in CPU design (it's been around in ASIC design for a bit longer). The cell libraries are often reused (though they're often process specific, so may change quite significantly), but Intel CPU families are usually complete new designs. The Pentium M was an exception, starting with the P3 and retrofitting the branch predictor and a few other things from the P4. ARM is similar, though they tend to have one team design a core and then get a second generation out of it by refining the design. There are some components that you might share between designs, but very often it's completely new.

    --
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