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posted by janrinok on Tuesday June 02 2015, @01:53PM   Printer-friendly
from the big-business dept.

Two members of our community have submitted information on the Intel purchase of Altera:

Intel To Buy Altera For 16.7 billion USD

Intel bought chipmaker Altera for 16.7 billion US$. This follows another huge purchase in the semiconductor industry last week, when Avago snapped up Broadcom for $37 billion US$. This has been a record year for consolidation within the industry, as companies struggle to deal with slowing growth and stagnating stock prices. Altera had already rejected an offer from Intel, but shareholders pressured them to reconsider. "Acquiring Altera may help Intel defend and extend its most profitable business: supplying server chips used in data centers. While sales of semiconductors for PCs are declining as more consumers rely on tablets and smartphones to get online, the data centers needed to churn out information and services for those mobile devices are driving orders for higher-end Intel processors and shoring up profitability. Altera has a huge FPGA business.

Perhaps this will impact Altera FPGA Linux support?

Intel Acquires Altera for $16.7 Billion

Intel Corporation has announced that it is buying Altera Corporation for $16.7 billion in cash. The deal will allow Intel to access potentially valuable field-programmable gate array (FPGA) revenue streams and integrate FPGAs into Xeon chips to try and maintain its dominance in datacenters. Altera has already been using Intel's 14nm process to make its Stratix FPGAs.

The Platform has more in-depth analysis of the deal:

The first hedge that Intel is making with the Altera acquisition is that a certain portion of the compute environment that it more or less owns in the datacenter will shift from CPUs to FPGAs.

In the conference call announcing the deal for Altera, Intel CEO Brian Krzanich said that up to a third of cloud service providers – what we here at The Platform call hyperscalers – could be using hybrid CPU-FPGA server nodes for their workloads by 2020. (This is an Intel estimate.) Intel's plan is to get a Xeon processor and an Altera FPGA on the same chip package by the end of 2016 – Data Center Group general manager Diane Bryant showed off a prototype of such a device in early 2014 – and ramp its production through 2017, with a follow-on product that actually puts the CPU and the FPGA circuits on the same die in monolithic fashion "shortly after that."

Intel plans to create a hybrid Atom-FPGA product aimed at the so-called Internet of Things telemetry market, and this will be a monolithic design as well, according to Krzanich; the company is right now examining whether it needs an interim Atom and FPGA product that shares a single package but are not etched on a single die.


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  • (Score: 3, Informative) by kaszz on Tuesday June 02 2015, @08:47PM

    by kaszz (4211) on Tuesday June 02 2015, @08:47PM (#191264) Journal

    Implementing a CPU in FPGA requires more gates than said CPU because the FPGA needs a configuration support structure. And the latency between those gates will be slower than said CPU. So if one implements a CPU on FPGA and runs a video compression codec. It will be slower.

    The nice thing about FPGA is that you can implement the codec directly as a gate structure. In that situation you have no CPU, but a codec that runs way faster than most CPUs can even dream of. Also if you need to handle I/O at high speed. An FPGA can easily clock bit by bit in 2 ns. Something most CPUs just can't do without a specific sub circuitry, which makes it loose flexibility.

    So if you use a wrench to hammer nails. It will work but it's suboptimal. If you use it for the right task, it's awesome.

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  • (Score: 4, Informative) by bob_super on Tuesday June 02 2015, @09:10PM

    by bob_super (1357) on Tuesday June 02 2015, @09:10PM (#191274)

    Pretty much this.

    I deal with FPGA on a daily basis. You don't use them for sequential CPU operations, you use them for parallel pipelined processing. If the clock seems slow at only 400MHz, it also that means you're pipelining a new chunk of data every 2.5ns. Apply this to a 1000-bit-wide bus, and suddenly you're processing a 400Gb/s Ethernet pipe in real time. Good luck doing that with a CPU.
    The same consideration applies to running multiple filters in real-time on HD/4k video and compressing it. CPUs can do it, but you won't like the electric bill. FPGAs love that stuff.

    Of course, an ASIC gives you higher performance and less power than the same logic in FPGA gates. But the ginormous upfront cost and time-to-market restrict ASICs to cost-sensitive high-volume applications.