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posted by janrinok on Friday July 17 2015, @10:00AM   Printer-friendly
from the hickory-dickory-dock dept.

Intel's "Tick-Tock" strategy of micro-architectural changes followed by die shrinks has officially stalled. Although Haswell and Broadwell chips have experienced delays, and Broadwell desktop chips have been overshadowed by Skylake, delays in introducing 10nm process node chips have resulted in Intel's famously optimistic roadmap missing its targets by about a whole year. 10nm Cannonlake chips were set to begin volume production in late 2016, but are now scheduled for the second half of 2017. In its place, a third generation of 14nm chips named "Kaby Lake" will be launched. It is unclear what improvements Kaby Lake will bring over Skylake.

Intel will not be relying on the long-delayed extreme ultraviolet (EUV) lithography to make 10nm chips. The company's revenues for the last quarter were better than expected, despite the decline of the PC market. Intel's CEO revealed the stopgap 14nm generation at the Q2 2015 earnings call:

"The lithography is continuing to get more difficult as you try and scale and the number of multi-pattern steps you have to do is increasing," [Intel CEO Brian Krzanich] said, adding, "This is the longest period of time without a lithography node change."

[...] But Krzanich seemed confident that letting up on the gas, at least for now, is the right move – with the understanding that Intel will aim to get back onto its customary two-year cycle as soon as possible. "Our customers said, 'Look, we really want you to be predictable. That's as important as getting to that leading edge'," Krzanich said during Wednesday's earnings call. "We chose to actually just go ahead and insert – since nothing else had changed – insert this third wave [with Kaby Lake]. When we go from 10-nanometer to 7-nanometer, it will be another set of parameters that we'll reevaluate this."

Intel Roadmap
Year   Old   New
2014   14nm Broadwell   14nm Broadwell
2015   14nm Skylake   14nm Skylake
2016   10nm Cannonlake   14nm Kaby Lake
2017   10nm "Tock"   10nm Cannonlake
2018   N/A   10nm "Tock"


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  • (Score: 0) by Anonymous Coward on Friday July 17 2015, @10:08AM

    by Anonymous Coward on Friday July 17 2015, @10:08AM (#210367)

    This delay may give them more time to catch up in the die shrinking game. This is good news for competition.

  • (Score: 0) by Anonymous Coward on Friday July 17 2015, @10:19AM

    by Anonymous Coward on Friday July 17 2015, @10:19AM (#210370)

    AMD's projected new chips won't be out for another year or two anyway, meaning they will be out just in time to be behind the curve yet again. And last I checked none of them were expected to be on a new process (IE still 28 nm... 3 years later?)

    • (Score: 1, Insightful) by Anonymous Coward on Friday July 17 2015, @10:54AM

      by Anonymous Coward on Friday July 17 2015, @10:54AM (#210373)

      Which is probably a big factor in why Intel chose to delay. Why push yourself if no one else is pushing either?

    • (Score: 4, Interesting) by takyon on Friday July 17 2015, @11:45AM

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday July 17 2015, @11:45AM (#210382) Journal

      Zen is scheduled to come out next year, deliver a massive 40% IPC improvement [anandtech.com] (feasible because of Bulldozer's bad architecture), and will apparently be skipping 20nm and going directly to 14nm [wccftech.com]. Some of its APUs may come with high bandwidth memory 2.0 next year.

      On GPUs AMD is much more comparable to NVIDIA than AMD w/ Intel on CPUs. Both AMD and NVIDIA will use high bandwidth memory 2.0 next year, and will probably boost HBM DRAM past 4 GB on most cards. Both companies may skip to 14nm. There have been reports that AMD will quickly release something on 20nm during 2015-2016.

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    • (Score: 3, Interesting) by dusty monkey on Friday July 17 2015, @02:02PM

      by dusty monkey (5492) on Friday July 17 2015, @02:02PM (#210428)

      The process size of all foundries have been lies for years now. For instance the smallest gate lengths in intels 22nm tri-gate process (ivy bridge) were actually 25nm, and thats on the entire chip. Not a single gate length less than 25nm in its "22nm" chips.

      How is it 22nm then? It isn't. Pure and simple. Its all marketing babble now.

      AMD is still stuck using gloflo's finfets, and even when gloflo starts pushing out their so called 14nm finfets in 2016 based on some cross-licenses samsung technology, the smallest gate length on the chips will be 20nm. I am guessing that intel is still stuck near ~20nm gate lengths also.

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      • (Score: 2) by takyon on Friday July 17 2015, @07:31PM

        by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday July 17 2015, @07:31PM (#210556) Journal

        It may be misleading and each manufacturer may have their own definition of 32/28/22/20/16/14/10/7 nm, but it doesn't matter much.

        What matters is that a.) it is harder to make components smaller, b.) they are making components smaller, and c.) there are benefits (cost, performance, power consumption, size) to making it smaller.

        When IBM announced the 7nm demo, they emphasized that the FinFETs were stacked at a pitch of less than 30nm, compared to 42nm for Broadwell.

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