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posted by janrinok on Friday July 31 2015, @12:43PM   Printer-friendly
from the cough-choke dept.

The 3D design uses a transistor-less cross point architecture to create a 3D design of interconnects, where memory cells sit at the intersection of word lines and bit lines, allowing the cells to be addressed individually. This means data can be read or written to and from the actual cells containing data and not the whole chip containing relevant cells.

Beyond that, though, we don't know much about the memory, like exactly what kind of memory it is. Is it phase change memory, ReRAM, MRAM or some other kind of memory? The two won't say. The biggest unanswered question in my mind is the bus for this new memory, which is supposed to start coming to market next year. The SATA III bus used by virtually all motherboards is already considered saturated. PCI Express is a faster alternative assuming you have the lanes for the data.

Making memory 1000 times faster isn't very useful if it chokes on the I/O bus, which is exactly what will happen if they use existing technology. It would be like a one-lane highway with no speed limit.

It needs a new use model. It can't be positioned as a hard drive alternative because the interfaces will choke it. So the question becomes what do they do? Clearly they need to come up with their own bus. Jim Handy, an analyst who follows the memory space, thinks it will be an SRAM interface. SRAM is used in CPU caches. This would mean the 3D XPoint memory would talk directly to the CPU.

"The beauty of an SRAM interface is that its really, really fast. What's not nice is it has a high pin count," he told me.

He also likes the implementation from Diablo Technologies, which basically built SSD drives in the shape of DDR3 memory sticks that plug into your motherboard memory slots. This lets the drives talk to the CPU at the speed of memory and not a hard drive.

One thing is for sure, the bus will be what makes or breaks 3D XPoint, because what good is a fast read if it chokes on the I/O interface?


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  • (Score: 3, Insightful) by cloud.pt on Friday July 31 2015, @01:07PM

    by cloud.pt (5516) on Friday July 31 2015, @01:07PM (#216286)

    This is Intel and Micron we are talking about. I don't think they'll have a problem designing a faster bus to take advantage of this memory performance increase. You must take into account two things: for starters, most bus'es nowadays have been made with the bottleneck of I/O devices in mind, not the other way around, because usually it's not the bus that bottlenecks. Now they can really create something that takes into consideration the main functionality of a good bus - raw throughput; and once again, we are talking about Intel and Micron here - besides CPUs and Flash Drives, their main market, they make motherboard reference designs, chipset architectures and I/O controllers on both endpoints. They are both arguably in the top 3 companies on ALL those subjects by units shipped and performance achieved. Are you really bothering they will have trouble using such technology? That's like giving a sniper rifle with 100% accurate automatic target tracking to the best sniper in the world, and saying he won't be able to put it to use because his primary skill is no longer worth a dime. Trust me, nobody is the best at anything without being pretty damn good in a lot of stuff around that particular subject.

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