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posted by janrinok on Friday July 31 2015, @12:43PM   Printer-friendly
from the cough-choke dept.

The 3D design uses a transistor-less cross point architecture to create a 3D design of interconnects, where memory cells sit at the intersection of word lines and bit lines, allowing the cells to be addressed individually. This means data can be read or written to and from the actual cells containing data and not the whole chip containing relevant cells.

Beyond that, though, we don't know much about the memory, like exactly what kind of memory it is. Is it phase change memory, ReRAM, MRAM or some other kind of memory? The two won't say. The biggest unanswered question in my mind is the bus for this new memory, which is supposed to start coming to market next year. The SATA III bus used by virtually all motherboards is already considered saturated. PCI Express is a faster alternative assuming you have the lanes for the data.

Making memory 1000 times faster isn't very useful if it chokes on the I/O bus, which is exactly what will happen if they use existing technology. It would be like a one-lane highway with no speed limit.

It needs a new use model. It can't be positioned as a hard drive alternative because the interfaces will choke it. So the question becomes what do they do? Clearly they need to come up with their own bus. Jim Handy, an analyst who follows the memory space, thinks it will be an SRAM interface. SRAM is used in CPU caches. This would mean the 3D XPoint memory would talk directly to the CPU.

"The beauty of an SRAM interface is that its really, really fast. What's not nice is it has a high pin count," he told me.

He also likes the implementation from Diablo Technologies, which basically built SSD drives in the shape of DDR3 memory sticks that plug into your motherboard memory slots. This lets the drives talk to the CPU at the speed of memory and not a hard drive.

One thing is for sure, the bus will be what makes or breaks 3D XPoint, because what good is a fast read if it chokes on the I/O interface?


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  • (Score: 5, Insightful) by TheRaven on Friday July 31 2015, @01:40PM

    by TheRaven (270) on Friday July 31 2015, @01:40PM (#216301) Journal

    First, Intel is claiming DRAM, or close-to-DRAM speeds. That means that you're likely to see it in DIMM slots, which have ample bandwidth. All you need is a CPU that has the correct instructions to ensure that cache lines have been flushed to the persistent memory. Guess which major CPU vendor added these instructions to their CPUs a couple of years ago.

    Second, Flash SSDs can usually saturate the SATA bus when it comes to sequential reads. For random writes, they're an order of magnitude or so better than spinning rust, but they're a long way away from bus speed. If you're doing anything other than running contrived benchmarks, there's a lot of spare speed in SATA for a faster SSD.

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  • (Score: 2) by theluggage on Friday July 31 2015, @02:12PM

    by theluggage (1797) on Friday July 31 2015, @02:12PM (#216313)

    Exactly. People seem to have missed that this is INTEL. You may have heard of them - they design and make rather popular processors and the key chipsets for rather popular motherboards. Hmm... how are they going to solve the problem of current CPUs, motherboards & chipsets not supporting XPOINT memory?

    Wouldn't it be terrible for Intel if everybody needed to buy new CPUs and motherboards to get an XPOINT intermediate storage slot? They'd be especially gutted if XPOINT wasn't available on AMD or ARM...