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posted by janrinok on Friday July 31 2015, @12:43PM   Printer-friendly
from the cough-choke dept.

The 3D design uses a transistor-less cross point architecture to create a 3D design of interconnects, where memory cells sit at the intersection of word lines and bit lines, allowing the cells to be addressed individually. This means data can be read or written to and from the actual cells containing data and not the whole chip containing relevant cells.

Beyond that, though, we don't know much about the memory, like exactly what kind of memory it is. Is it phase change memory, ReRAM, MRAM or some other kind of memory? The two won't say. The biggest unanswered question in my mind is the bus for this new memory, which is supposed to start coming to market next year. The SATA III bus used by virtually all motherboards is already considered saturated. PCI Express is a faster alternative assuming you have the lanes for the data.

Making memory 1000 times faster isn't very useful if it chokes on the I/O bus, which is exactly what will happen if they use existing technology. It would be like a one-lane highway with no speed limit.

It needs a new use model. It can't be positioned as a hard drive alternative because the interfaces will choke it. So the question becomes what do they do? Clearly they need to come up with their own bus. Jim Handy, an analyst who follows the memory space, thinks it will be an SRAM interface. SRAM is used in CPU caches. This would mean the 3D XPoint memory would talk directly to the CPU.

"The beauty of an SRAM interface is that its really, really fast. What's not nice is it has a high pin count," he told me.

He also likes the implementation from Diablo Technologies, which basically built SSD drives in the shape of DDR3 memory sticks that plug into your motherboard memory slots. This lets the drives talk to the CPU at the speed of memory and not a hard drive.

One thing is for sure, the bus will be what makes or breaks 3D XPoint, because what good is a fast read if it chokes on the I/O interface?


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  • (Score: 2) by takyon on Friday July 31 2015, @03:53PM

    by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday July 31 2015, @03:53PM (#216354) Journal

    http://m.theregister.co.uk/2015/07/30/xpoint_cuckoo_invades_memory_storage_hierarchy_nest/ [theregister.co.uk]

    FlashDIMMS are shown in the same region as XPoint. Until we know actual XPoint speeds, we can't be any more precise than that. SAS and SATA SSDs are pushing into the 10,000rpm disk drive space, with 3D TLC (3bits/cell) NAND being at the forefront of this.

    XPoint memory is up to 1,000 times faster than NAND, but it can barely reach 20 per cent of the speeds DRAM is capable of. This may mean that a SATA-connected XPoint SSD will have a large proportion of its access latency taken up by the SATA interface, and also that current state-of-the-art 12Gbit/s SATA restricts its bandwidth.

    It will not cost as much as DRAM but will cost more than NAND. Actual prices don't exist yet and we have not seen relative cost multiples, such as XPoint will be five times more costly than NAND, but half the price of DRAM.

    DIMMs would seem to be a good place for XPoint. Companies like Diablo are putting NAND in DIMMs.

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