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Raymond Chen recently posted a ten-part introduction to the ia64 architecture. Rapidly teaching me that while I might be able to write a brainfuck to perl compiler in a few minutes, there's no way in a million years that I'll ever be able to write a good compiler that targets ia64.
- Part 1: Warming up
- Part 2: Instruction encoding, templates, and stops
- Part 3: The Windows calling convention, how parameters are passed
- Part 3b: How does spilling actually work?
- Part 4: The Windows calling convention, leaf functions
- Part 5: The GP register, calling functions, and function pointers
- Part 6: Calculating conditionals
- Part 7: Speculative loads
- Part 8: Advanced loads
- Part 9: Counted loops and loop pipelining
- Part 10: Register rotation
The Itanium is a 64-bit EPIC architecture. EPIC stands for Explicitly Parallel Instruction Computing, a design in which work is offloaded from the processor to the compiler. For example, the compiler decides which operations can be safely performed in parallel and which memory fetches can be productively speculated. This relieves the processor from having to make these decisions on the fly, thereby allowing it to focus on the real work of processing.
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Fascinating is a word I use for the unexpected.
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(Score: 0) by Anonymous Coward on Sunday August 09 2015, @12:15AM
> The issue was intel only using their 'legacy' processes to produce itanium chips and not providing 'entry level' systems to gain the software developer mindshare with.
Because they thought they could own the market - they were caught unaware by x86 moving into the workstation and server space. Itanium was intended to kill MIPS/SPARC/POWER and replace PA. Instead x86-64 took marketshare from all of them and Itanium was left with a tiny piece of the pie - for chips that cost a fuckload to manufacture.
> it only makes sense if you have a lot of PA-RISC experience to begin with, which was even more niche than itanium.
Eh. The joke was that itanium was PA-3.0. But all the stuff that made EPIC hard was brand new. PA-2.0 was a pretty typical RISC, not terribly different from the other RISC architectures of the day.
(Score: 3, Interesting) by turgid on Sunday August 09 2015, @11:37AM
Back in 1999 when there were still several CPU architectures to choose from (before itanic hype killed them off) Sun did a port of Solaris to itanic. It didn't take long since the Solaris code base was pretty portable, however Sun didn't want to kill off SPARC so it was never released. It's a shame that Sun wasn't very good at getting it's own CPUs out. Look at what Fujitsu was able to achieve with SPARC...
I refuse to engage in a battle of wits with an unarmed opponent [wikipedia.org].