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posted by mrcoolbp on Tuesday May 12 2015, @06:00AM   Printer-friendly
from the factory-is-probably-already-compromised-by-NSA dept.

The Moscow Center for SPARC Technologies has released a quad-core chip built on a 65 nm process:

Despite the company's own name, the chip is actually built on the proprietary "Elbrus" instruction set architecture and not on SPARC. The CPU cores are clocked only at 800 MHz each, and the chip is manufactured on a rather old 65 nm process. The chip has a TDP of 45 W, which isn't too bad considering its target market [of high-performance PCs and servers].

However, the performance may be lacking. Going by the MCST's own benchmarks (shown above and below), the CPU is only compared with older Atom chips that used to target netbooks or (also old) "Pentium-M" notebook processors. Even if the Elbrus-4C wins by a large margin in the floating point score, it does so against obsolete processors. When it is compared against the others for integer performance, the difference is much smaller.

The Register speculates that this chip may be the first effort to wean Russia off of "compromised" Intel and AMD processors.

The Elbrus 4c used in the PCs and servers is said to support two instruction sets: very long instruction word and SPARC. It's also said to be capable of x86 emulation, and to run Linux natively, after one performs binary translation.

The Elbrus ARM-401 PC is a minitower packing a version of Linux also called Elbrus and boasts four USB 2.0 ports, a PCI-express slot, gigabit ethernet and not much more. The CPU is apparently capable of running Doom 3, enabling Russian gamers to go fragging like it's 2004.

The Server Elbrus 4.4 is a four-socket affair and four of the machines fit into a 1U chassis. Gigabit ethernet, SATA and plenty of PCI slots connect it to other kit and the rest of the worlds.

MCST has announced the products are on sale, but don't expect an online configurator at which you can run up a rig and get a live price: the outfit offers just the sales@mcst.ru email address for would-be buyers.

Related Stories

Zhaoxin KaiXian KX-6000: A Chinese x86 SoC 29 comments

Zhaoxin Displays x86-Compatible KaiXian KX-6000: 8 Cores, 3 GHz, 16 nm FinFET

Zhaoxin, a joint venture between Via Technologies and the Chinese government, this week for the first time displayed its upcoming x86-compatible CPU, the KaiXian KX-6000. The SoC features eight cores running at 3 GHz and increases performance over its predecessor by at least 50%.

The KaiXian KX-6000 is a successor to the KX-5000 CPU launched earlier this year. Both chips integrate eight-core x86-64 cores with 8 MB of L2 cache, a DirectX 11.1-capable iGPU with an up-to-date display controller, a dual-channel DDR4-3200 memory controller, contemporary I/O interfaces (PCIe, SATA, USB, etc), and so on. The key differences between the KaiXian KX-5000 and the KaiXian KX-6000 are frequencies and manufacturing technology: the former is produced using TSMC's 28 nm fabrication process and runs at up to 2 GHz, whereas the latter is made using TSMC's 16 nm technology and operates at up to 3 GHz. Zhaoxin claims that the Kaixian KX-6000 offers compute performance comparable to that of Intel's 7th Generation Core i5 processor, which is a quad-core non-Hyper-Threaded CPU. Obviously, performance claims like that have to be verified, yet a 50% performance bump over the direct predecessor already seems beefy enough.

Related: Russia Plans to Dump Some American CPUs for Homegrown Technology
Russian Homegrown Elbrus-4C CPU Released
U.S. Export Restrictions Lead to Chinese Homegrown Supercomputing Chips
Linux-Based, MIPS-Powered Russian All-in-One PC Launched
China Dominates TOP500 List, Leads With New 93 Petaflops Supercomputer
Chinese Company Produces Chips Closely Based on AMD's Zen Microarchitecture


Original Submission

Programming Guide for Russia's "28nm" Elbrus-8CB CPU Published 16 comments

Russia's Elbrus 8CB Microarchitecture: 8-core VLIW on TSMC 28nm

All of the world's major superpowers have a vested interest in building their own custom silicon processors. The vital ingredient to this allows the superpower to wean itself off of US-based processors, guarantee there are no supplemental backdoors, and if needed add their own. As we have seen with China, custom chip designs, x86-based joint ventures, or Arm derivatives seem to be the order of the day. So in comes Russia, with its custom Elbrus VLIW design that seems to have its roots in SPARC.

Russia has been creating processors called Elbrus for a number of years now. For those of us outside Russia, it has mostly been a big question mark as to what is actually under the hood – these chips are built for custom servers and office PCs, often at the direction of the Russian government and its requirements. We have had glimpses of the design, thanks to documents from Russian supercomputing events, however these are a few years old now. If you are not in Russia, you are unlikely to ever get your hands on one at any rate. However, it recently came to our attention of a new programming guide listed online for the latest Elbrus-8CB processor designs.

The latest Elbrus-8CB chip, as detailed in the new online programming guide published this week, built on TSMC's 28nm, is a 333 mm2 design featuring 8 cores at 1.5 GHz. Peak throughput according to the documents states 576 GFLOPs of double precision, with the chip offering four channels of DDR4-2400, good for 68.3 GB/s. The L1 and L2 caches are private, with a 64 kB L1-D cache, a 128 kB L1-I cache, and a 512 kB L2 cache. The L3 cache is shared between the cores, at 2 MB/core for a total of 16 MB. The processor also supports 4-way server multiprocessor combinations, although it does not say on what protocol or what bandwidth.

It is a compiler focused design, much like Intel's Itanium, in that most of the optimizations happen at the compiler level. Based on compiler first designs in the past, that typically does not make for a successful product. Documents from 2015 state that a continuing goal of the Elbrus design is x86 and x86-64 binary translation with only a 20% overhead, allowing full support for x86 code as well as x86 operating systems, including Windows 7 (this may have been updated since 2015).

Previously: Russian Homegrown Elbrus-4C CPU Released


Original Submission

Russia to Build RISC-V Processors for Laptops: 8-core, 2 GHz, 12nm, 2025 15 comments

Russia To Build RISC-V Processors for Laptops: 8-core, 2 GHz, 12nm, 2025

Russian outlet Vedomosti.ru today is reporting that the conglomerate Rostec, a Russian state-backed corporation specializing in investment in technology, has penned a deal with server company Yadro and silicon design company Sintakor to develop RISC-V processors for computers, laptops, and servers. Initial reports are suggesting that Sintakor will develop a powerful enough RISC-V design to power government and education systems by 2025.

The cost of the project is reported to be around 30 billion rubles ($400m), with that the organizers of the project plan to sell 60,000 systems based around new processors containing RISC-V cores as the main processing cores. The reports state that the goal is to build an 8-core processor, running at 2 GHz, using a 12-nanometer process, which presumably means GlobalFoundries but at this point it is unclear. Out of the project funding, two-thirds will be provided by 'anchor customers' (such as Rostec and subsidiaries), while the final third will come from the federal budget. The systems these processors will go into will operate initially at Russia's Ministry of Education and Science, as well as the Ministry of Health.

Previously: Russian Homegrown Elbrus-4C CPU Released
Linux-Based, MIPS-Powered Russian All-in-One PC Launched
Programming Guide for Russia's "28nm" Elbrus-8CB CPU Published


Original Submission

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  • (Score: 3, Insightful) by jmorris on Tuesday May 12 2015, @06:15AM

    by jmorris (4844) on Tuesday May 12 2015, @06:15AM (#181813)

    Not going to make jokes about the performance (or lack of) of this new chip. The miracle is always getting a new design built at all, making an existing design go faster always seems to be more a matter of throwing more money at the problem. The question I'd want to ask is why the heck they built in two instruction sets. Seems that needlessly complicates the design and for a first attempt there would need to be a sound reason for it. SPARC isn't exactly a terrible ISA, it is licensable and the patent situation should even be fairly clean by now. Meanwhile VLIW hasn't exactly set the world on fire although it does seem to get used internally it seems like vendors hide it to avoid the problem of supporting the same one across product lines. Wonder if this isn't exactly the same situation and something is lost in translation?

    • (Score: 1, Informative) by Anonymous Coward on Tuesday May 12 2015, @06:33AM

      by Anonymous Coward on Tuesday May 12 2015, @06:33AM (#181821)

      (1) Nobody will use it or take it seriously if it isn't backward compatible with x86.
      (2) It's not a first attempt or even a new design; Elbrus dates back to 1973. [wikipedia.org]

    • (Score: 0) by Anonymous Coward on Tuesday May 12 2015, @07:03AM

      by Anonymous Coward on Tuesday May 12 2015, @07:03AM (#181833)

      The miracle is always getting a new design built at all, making an existing design go faster always seems to be more a matter of throwing more money at the problem.

      If that's the case they should license and use ARM stuff. That way it's not just them throwing money at the problem but others around the world.

    • (Score: 3, Informative) by TheRaven on Tuesday May 12 2015, @08:40AM

      by TheRaven (270) on Tuesday May 12 2015, @08:40AM (#181865) Journal

      The miracle is always getting a new design built at all, making an existing design go faster always seems to be more a matter of throwing more money at the problem

      Code reuse is still a very new concept in CPU design (it's been around in ASIC design for a bit longer). The cell libraries are often reused (though they're often process specific, so may change quite significantly), but Intel CPU families are usually complete new designs. The Pentium M was an exception, starting with the P3 and retrofitting the branch predictor and a few other things from the P4. ARM is similar, though they tend to have one team design a core and then get a second generation out of it by refining the design. There are some components that you might share between designs, but very often it's completely new.

      --
      sudo mod me up
  • (Score: 0) by Anonymous Coward on Tuesday May 12 2015, @06:23AM

    by Anonymous Coward on Tuesday May 12 2015, @06:23AM (#181814)

    32-bit Doom3 is so 2004.

  • (Score: 2, Informative) by Anonymous Coward on Tuesday May 12 2015, @06:25AM

    by Anonymous Coward on Tuesday May 12 2015, @06:25AM (#181816)

    User "eSyr" writes:
    "By the way, "ARM" in "Elbrus ARM-401" is a cyrillic abbreviation which roughly stands for "automated (computer-assisted) work place" («АРМ» — «автоматизированное рабочее место» in russian). It is common to call workstation/desktop-class machines (together with associated periphery) like this in government/military official documentation."
    -http://arstechnica.com/gadgets/2015/05/russia-now-selling-home-grown-cpus-with-transmeta-like-x86-emulation/?comments=1&start=0

    On SPARC:
    User "enduzzer" writes:
    Here's some more info on Moscow Center for SPARC Technologies. The New York Times (1992).

    http://www.nytimes.com/1992/09/02/business/company-news-russian-research-pact-for-sun-microsystems.html [nytimes.com]

    The new agreement follows a joint research project that Sun announced with the Russian researchers in February. Those efforts have led to the establishment of a research center in Russia called the Moscow Center of Sparc Technology. Sparc is the name of the microprocessor chip technology on which Sun's work stations are based.

    • (Score: 0) by Anonymous Coward on Tuesday May 12 2015, @06:28AM

      by Anonymous Coward on Tuesday May 12 2015, @06:28AM (#181818)

      181818?

      • (Score: 0) by Anonymous Coward on Tuesday May 12 2015, @06:40AM

        by Anonymous Coward on Tuesday May 12 2015, @06:40AM (#181822)

        18spooky18me

        • (Score: -1, Troll) by Anonymous Coward on Tuesday May 12 2015, @06:43AM

          by Anonymous Coward on Tuesday May 12 2015, @06:43AM (#181824)

          niggerniggerspooknigger

      • (Score: 0) by Anonymous Coward on Tuesday May 12 2015, @09:17AM

        by Anonymous Coward on Tuesday May 12 2015, @09:17AM (#181878)

        Got your number...

    • (Score: 2) by kaszz on Tuesday May 12 2015, @08:48AM

      by kaszz (4211) on Tuesday May 12 2015, @08:48AM (#181869) Journal

      Isn't Sun Microsystems, Inc gone? as in absorbed by Oracle?

      (which seem to produce sloppy code)

  • (Score: 1, Insightful) by Anonymous Coward on Tuesday May 12 2015, @06:43AM

    by Anonymous Coward on Tuesday May 12 2015, @06:43AM (#181823)

    No vPro/VT/Intel-AMT/whatever-they-change-the-name-to-next back door?
    No chipset level OS agnostic VNC server that pulls from integrated framebuffer?
    No uploading ram contents through the network or 3g?
    No always-able-to-reenable-disabled-backdoor?

    Why doesn't anyone kill the engineers and managers at Intel who added the backdoors in a cruel manner by device?

    • (Score: 1, Touché) by Anonymous Coward on Tuesday May 12 2015, @06:49AM

      by Anonymous Coward on Tuesday May 12 2015, @06:49AM (#181828)

      Why doesn't anyone kill the engineers and managers at Intel who added the backdoors in a cruel manner by device?

      Why haven't you killed them yet? Too busy doing what you're told when you're told because you're told?

      • (Score: 0) by Anonymous Coward on Tuesday May 12 2015, @07:50AM

        by Anonymous Coward on Tuesday May 12 2015, @07:50AM (#181848)

        >Why haven't you killed them yet? Too busy doing what you're told when you're told because you're told?

        Yes. I obey. Everything I want is banned.

    • (Score: 2) by mtrycz on Tuesday May 12 2015, @07:50AM

      by mtrycz (60) on Tuesday May 12 2015, @07:50AM (#181849)

      We'll need an open source processor for that.

      Someday.

      --
      In capitalist America, ads view YOU!
      • (Score: 0) by Anonymous Coward on Tuesday May 12 2015, @08:27AM

        by Anonymous Coward on Tuesday May 12 2015, @08:27AM (#181858)

        Just need a heavy object.

        Or a wheel and an iron bar.

  • (Score: -1, Offtopic) by Anonymous Coward on Tuesday May 12 2015, @06:45AM

    by Anonymous Coward on Tuesday May 12 2015, @06:45AM (#181825)

    Does russia like young girls?

    What about old testament pro-marry-young-girls opinion?

    What about killing feminists?

  • (Score: 3, Interesting) by MichaelDavidCrawford on Tuesday May 12 2015, @06:46AM

    whenever a smaller process is introduced, a lot of phenomenally expensive fab equipment becomes obsolete. By using a 65 nm process, this chip can be manufactured by fabs that might otherwise be sitting idle.

    ARM cores are that way too - they are designed in such a way that you can make them with yesterday's fabs.

    --
    Yes I Have No Bananas. [gofundme.com]
    • (Score: 2, Funny) by Anonymous Coward on Tuesday May 12 2015, @06:53AM

      by Anonymous Coward on Tuesday May 12 2015, @06:53AM (#181831)

      I'm using a 65 nm processor right now! Finally, I'm trendy again.

      • (Score: 3, Funny) by FatPhil on Tuesday May 12 2015, @12:31PM

        by FatPhil (863) <{pc-soylent} {at} {asdf.fi}> on Tuesday May 12 2015, @12:31PM (#181909) Homepage
        Writing this on a G5 workstation with a 90nm process, NATted through a x86 (32 bit) crate with a 130nm process.

        Don't make me wave my 8" floppies around - I might take someone's eye out!
        --
        Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves
    • (Score: 3, Interesting) by MichaelDavidCrawford on Tuesday May 12 2015, @07:28AM

      Even if the circuit schematic were identical, the physical design of chips with smaller feature sizes are significantly different. Once a new process becomes available, it's a significant amount of work for the hardware designers to shrink their designs.

      I studied analog and digital electronics at UCSC, but in a course taught by the physics department meant to enable us to design and build our own experimental apparatus. The analog professor, David Dorfan - and a rather outspoken fellow - pointed out that analog was not required for a EE degree. "I can see how they can design their circuits," he griped, "but I don't understand how they can get them to work."

      I myself cured a Solaris server hang by replacing a whole bunch of serial cables, with cables that had lower capacitance per unit lengths, this because of capacitive coupling that led the login prompt to be regarded as the username. The detective work was quite cool but I don't have the headspace to explain it just now.

      --
      Yes I Have No Bananas. [gofundme.com]
      • (Score: 2) by CoolHand on Tuesday May 12 2015, @11:31AM

        by CoolHand (438) on Tuesday May 12 2015, @11:31AM (#181900) Journal

        The analog professor, David Dorfan - and a rather outspoken fellow - pointed out that analog was not required for a EE degree. "I can see how they can design their circuits," he griped, "but I don't understand how they can get them to work."

        Did you mean he was your digital professor? That quote would make a lot more sense to me if so.. If not, then to whom does "they" refer in his quote? The digital people?

        --
        Anyone who is capable of getting themselves made President should on no account be allowed to do the job-Douglas Adams
        • (Score: 0) by Anonymous Coward on Tuesday May 12 2015, @02:58PM

          by Anonymous Coward on Tuesday May 12 2015, @02:58PM (#181952)

          I guess the analog professor wondered how the digital people could get their circuits to work without having learned the analog stuff.

    • (Score: 3, Insightful) by gnuman on Tuesday May 12 2015, @03:43PM

      by gnuman (5013) on Tuesday May 12 2015, @03:43PM (#181970)

      By using a 65 nm process, this chip can be manufactured by fabs that might otherwise be sitting idle.

      It is very unlikely these things sit idle. There are tons of "low speed" ICs that need to be manufactured.

  • (Score: 0) by Anonymous Coward on Tuesday May 12 2015, @06:50AM

    by Anonymous Coward on Tuesday May 12 2015, @06:50AM (#181830)
    • (Score: 1, Informative) by Anonymous Coward on Tuesday May 12 2015, @06:57AM

      by Anonymous Coward on Tuesday May 12 2015, @06:57AM (#181832)
      • (Score: 0) by Anonymous Coward on Tuesday May 12 2015, @07:43AM

        by Anonymous Coward on Tuesday May 12 2015, @07:43AM (#181847)

        In the linked game everything free/opensource, including the media.