Intel's Knights-branded Xeon Phi chips remain the most familiar "many-core" accelerators or coprocessors. However, another name has emerged recently: PEZY, whose 1,024-core chips were used in the top 3 most efficient supercomputers. Tom's Hardware reports that PEZY's next generation of chips will boost the core count to 4,096 and integrate Imagination's 64-bit MIPS Warrior CPU onto a system-on-a-chip:
PEZY Computing, a Japanese firm that makes the top three most efficient supercomputers in the world, according to the Green500 list, announced that it will integrate Imagination's highly efficient 64-bit I6400 CPUs into its many-core architecture.
The PEZY SC-2 will be PEZY's next-generation system, which will increase the 1024 core count of the first generation PEZY SC to 4096 cores, or four times more. PEZY's many-core accelerator has been combined with Intel CPUs from top supercomputers to significantly increase their efficiency for computing tasks. For instance, the Shoubo supercomputer, which uses Haswell XEON CPUs and PEZY SC many-core accelerators, was able to break the world record with 7 GFLOPS/W performance.
In the November edition of Green500, the top 23 supercomputers used a heterogeneous architecture with many-core accelerators. In the updated June edition of this year, that number increased by 40 percent, and now the top 32 supercomputers are using many-core accelerators. These supercomputers all use accelerators from AMD, Intel, Nvidia and PEZY. The current top 3 supercomputers are manufactured by PEZY Computing and Exascaler Inc, and include Haswell or Ivy Bridge Xeons as well as PEZY many-core accelerators.
Presumably the integration of the MIPS CPU could allow relatively power-hungry Intel Xeons to be ditched entirely.
Previously: MIPS Strikes Back: 64-bit Warrior I6400 Arrives
Related Stories
The recently Anandless AnandTech is reporting that Imagination Technologies/MIPS has ARM in their crosshairs.
Based on the 64-bit MIPS64 instruction set (release 6), the Warrior I6400 core is the middle-class CPU core in a family of three, each targeting a different point in the power/performance curve. Imagination is releasing the I6400 core last, which is at the middle of the pack balancing performance with power. Imagination has already released their high-end P56xx series and low-end M51xx series.
The June 2015 edition of the Green500 supercomputer list is finally out, and the top system, Shoubu at the Institute of Physical and Chemical Research (RIKEN) in Japan, has surpassed the 7 gigaflops per watt milestone. The following two systems surpassed 6 GFLOPS/W, and the current #4 system led the November 2014 list at 5.272 GFLOPS/W.
Shoubu is ranked #160 on the June 2015 edition of the TOP500 list, with an RMAX of 412.7 teraflops. Green500 reports its efficiency at 7,031.58 MFLOPS/W with a power consumption of 50.32 kW. The supercomputer uses Intel Xeon E5-2618Lv3 Haswell CPUs, "new many-core accelerators from PEZY-SC," and the InfiniBand data interconnect. The top 32 systems on the new Green500 list are heterogeneous, using GPU and "many-core" accelerators from the likes of AMD, Intel, NVIDIA, and PEZY Computing. The PEZY-SC accelerator used in the top 3 systems reportedly delivers 1.5 teraflops of double-precision floating-point performance using 1024 cores built on a 28nm process, while consuming just 90 W.
Green500 notes Japanese dominance in the supercomputer efficiency rankings. Aside from Shoubu at RIKEN, the #2 and #3 systems are located at the High Energy Accelerator Research Organization (KEK) in Tsukuba, Ibaraki, Japan. Eight of the top twenty systems on the newest Green500 list are located in Japan.
HPCwire reports on an analysis of the November 2015 TOP500 Supercomputer list by co-creator Dr. Erich Strohmaier showing "nothing wrong with Moore's Law". Strohmaier examined China's jump in installed systems and performance growth trends.
China's surge is mainly attributed to "surprise company" Sugon, which submitted smaller sytems. It achieved 3rd place in vendor market share, but just 7th in terms of installed performance, with 21 petaflops. Strohmaier says that Sugon was new to supercomputing and took the time and energy to run the LINPACK benchmark across all systems, "regardless of how well or badly they run and gave us the number". Lenovo became a Chinese company, and some "artifact" systems were labelled Lenovo/IBM or IBM/Lenovo. Strohmaier also pointed to Inspur with 15 systems.
Strohmaier identifies two inflection points in TOP500 performance development. The growth trajectory dips in 2008 and 2014, showing the effects of financial and technology changes. Turnover has decreased since 2008, with 1.27 year old systems before 2008 and roughly 3 year old systems today. However, by filtering out systems with NVIDIA and Xeon Phi coprocessors, Strohmaier identified an Rmax/socket trend that continues to follow Moore's Law and is the product of the average number of cores per socket and the performance per core. Since the performance per socket continues to increase at an exponential rate, it is the lack of growth in total number of sockets that explains TOP500 stagnation. "So it's clearly a technological reason, but it's not a reason on a chip, it's actually a reason on the facility and system level that is most likely related to either power or money or both."
[More after the break.]
The founder, President, and CEO of PEZY Computing, Motoaki Saito, has been arrested for allegedly defrauding the Japanese government:
The head of Japanese supercomputing firm PEZY Computing was arrested Tuesday on suspicion of defrauding a government institution of 431 million yen (~$3.8 million). According to reports in the Japanese press, PEZY founder, president and CEO Motoaki Saito and another PEZY employee, Daisuke Suzuki, are charged with profiting from padded claims they submitted to the New Energy and Industrial Technology Development Organization (NEDO).
On the 21st Green500 list, the top three most efficient supercomputers as well as the #5 most efficient supercomputer all use PEZY-SC2 "manycore" chips.
Previously: PEZY's Next Many-Core Chip Will Include a MIPS 64-Bit CPU
TOP500 Analysis Shows "Nothing Wrong with Moore's Law" and the November 2015 Green500 List
Shoubu Continues to Lead June 2016 Green500 List, World's Fastest Supercomputer Comes in at #3
Wave Computing Adopts Low Power MIPS 64-bit Multi-Threaded Core
Wave Computing [...] announced today that it has selected a 64-bit Multi-Threaded processor core from MIPS Technologies for future AI solutions. Wave will use the MIPS core in its next generation of Dataflow Processing Unit (DPU) chips that will ship in Wave's future deep learning systems to handle device control functions including management of the real-time operating system (RTOS) and system-on-chip (SoC) subsystem.
As design complexity and software footprints continue to increase, the 64-bit MIPS architecture is being used in an even broader set of datacenter, connected consumer devices, networking products, and emerging AI applications. In addition to Wave, companies including Mobileye, Fungible, ThinCI, and DENSO, among others, are using the MIPS 64-bit processor core as they develop ground-breaking AI applications. [...] Last August, Denso group company NSITEXE, Inc. announced that it licensed the newest MIPS CPU to drive enhanced in-vehicle electronic processing.
Related: MIPS Strikes Back: 64-bit Warrior I6400 Arrives
PEZY's Next Many-Core Chip Will Include a MIPS 64-Bit CPU
ARM Cortex-A35, Snapdragon 820, and New Imagination MIPS Processors
Linux-Based, MIPS-Powered Russian All-in-One PC Launched
Imagination Technologies Acquired for $675 Million, MIPS to be Sold Off
(Score: 1, Funny) by Anonymous Coward on Wednesday November 18 2015, @03:33AM
Yes, but will it run Irix? If not, who cares?
(Score: 4, Informative) by TheRaven on Wednesday November 18 2015, @09:21AM
For a supercomputer, this is probably fine. MIPS64r6 is a much nicer ISA than any previous MIPS and people who are spending tens of millions of dollars on a computer can probably be expected to recompile their code.
sudo mod me up
(Score: 2) by FatPhil on Wednesday November 18 2015, @06:02PM
That's a bit weird. For simplicity, did compiler writers just stuff the same instruction in the branch delay slot and the next address after the non-taken branch? (Namely a bit of the loop that should always be performed.) Sure, that's code bloat, but it's simple (it makes it behave more like a traditional branch delay slot, it's just you need 2 copies of the instruction).
However, any good MIPS news is good news. I'm a rabid anti-x86-ite! Shame that it's now in the hands of the bodgers at IMG, when I used to work alongside them they were useless f[rest of post elided, to keep blood pressure low]
Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves
(Score: 2) by TheRaven on Wednesday November 18 2015, @06:49PM
That's a bit weird. For simplicity, did compiler writers just stuff the same instruction in the branch delay slot and the next address after the non-taken branch?
Typically, you'll just hoist one instruction from the branch target into the delay slot. The idea was that it's easier to find an instruction to stuff in the delay slot if it only has to be from one target, not something that's useful for both targets. If the branch isn't taken, then you have to cancel that instruction, but no one cares because you're in the slow path (you've not taken a likely branch).
I'm a rabid anti-x86-ite!
If you're looking for a fun non-x86 platform, Cavium's ThunderX is really nice. They've been giving a few away for open source projects to play with.
sudo mod me up
(Score: 2) by FatPhil on Wednesday November 18 2015, @08:34PM
Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves
(Score: 0) by Anonymous Coward on Wednesday November 18 2015, @05:21AM
easy pezy japeneasy.