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posted by martyb on Wednesday March 16 2016, @12:43PM   Printer-friendly
from the 7000-picometers dept.

ARM Holdings and Taiwan Semiconductor Manufacturing Company (TSMC) have announced a collaboration on 7nm chips. They have already worked together to create CPUs at the 16nm and 10nm process nodes. There is no indication that extreme ultraviolet lithography (EUV) will be used for 7nm chips, whereas IBM used the technology for its 7nm demonstration chip last year:

IBM was the first to announce the creation of a 7nm chip, although the innovative processes it used to create it also meant that mass production wouldn't be possible for a few more years, due to the high cost. Chances are that IBM's 7nm chips could arrive sometime in 2018, or in 2019 at the latest.

Intel has already delayed its 10nm chip production to the second half of 2017, which means its 7nm chips won't arrive until late 2019, or even early 2020. That gives IBM and other companies the opportunity to surpass Intel in cutting-edge process technology for the first time.

It's not clear when TSMC will be mass-producing 7nm chips. However, knowing that its 10nm chips are likely to appear early next year, then chances are that its 7nm chips will be ready sometime in 2019, potentially surpassing Intel with quicker production of 7nm chips, too.

Also at The Register .


Original Submission

Related Stories

IBM and Partners Develop 7nm Process Chips 10 comments

Numerous sources are reporting that IBM's recent $3 billion investment in new chipmaking technologies and collaboration with the State University of New York in Albany, GlobalFoundries, and Samsung Electronics Co. is beginning to bear fruit. IBM has developed chips with functional transistors using a 7 nanometer process technology.

In particular, silicon-germanium (SiGe) has been incorporated into FinFET transistors, the fins of which are stacked at a pitch of less than 30nm, compared to a 42nm pitch for Intel's 14nm Broadwell chips. Long delayed extreme ultraviolet (EUV) lithography from ASML was used to etch the features. Although ASML's EUV tools are still slower and more expensive than conventional lithography, Michael Liehr, the executive vice president for innovation and technology at the SUNY Poly research center, predicted that ASML would improve EUV over the next four to six years, before 7nm chips are set to reach the market. More aggressive estimates put the introduction of 7nm chips around 2017-2018.

Ars Technica has a story on this topic with more technical background.


Original Submission

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  • (Score: 1, Informative) by Anonymous Coward on Wednesday March 16 2016, @01:11PM

    by Anonymous Coward on Wednesday March 16 2016, @01:11PM (#319009)

    The following article has a list of some other processors and their feature sizes. For example, the first Pentium processors were manufactured on an 800 nm process.

    http://www.elnexus.com/articles/45nm.aspx [elnexus.com]

    Nice going, TSMC!

    • (Score: 3, Insightful) by TheRaven on Thursday March 17 2016, @06:34AM

      by TheRaven (270) on Thursday March 17 2016, @06:34AM (#319461) Journal
      Somewhere, I have a copy of an issue of BYTE that has the new 1┬Ám process as the cover story. The full article talks about the imminent end to Moore's Law.
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  • (Score: 2) by bitstream on Wednesday March 16 2016, @01:18PM

    by bitstream (6144) on Wednesday March 16 2016, @01:18PM (#319011) Journal

    There might be a reason for the delay. Just consider the scale of these things! So any competitor will most likely have to face the same issues. Unless they have a whole another approach to the problem. The length is on the order of individual periods of x-rays and cellular walls.

    Btw, So when do they build a x-ray radio receiver? the technology to build the antenna seems almost ready..

  • (Score: 2) by fadrian on Wednesday March 16 2016, @02:00PM

    by fadrian (3194) on Wednesday March 16 2016, @02:00PM (#319025) Homepage

    Time to short?

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    • (Score: 4, Funny) by maxwell demon on Wednesday March 16 2016, @02:52PM

      by maxwell demon (1608) Subscriber Badge on Wednesday March 16 2016, @02:52PM (#319039) Journal

      Time to short?

      Given that a short only has 16 bits, it is not even long enough to hold the seconds of a single day. Therefore I strongly advice against using it for time.

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      The Tao of math: The numbers you can count are not the real numbers.
      • (Score: 0) by Anonymous Coward on Wednesday March 16 2016, @10:10PM

        by Anonymous Coward on Wednesday March 16 2016, @10:10PM (#319260)

        Given that a short only has 16 bits,

        Technically, all you're really guaranteed is that a short has at least as many bits as a char and no more than an int.

        • (Score: 0) by Anonymous Coward on Wednesday March 16 2016, @10:20PM

          by Anonymous Coward on Wednesday March 16 2016, @10:20PM (#319267)

          Technically, all you're really guaranteed is that a short has at least as many bits as a char and no more than an int.

          Not quite; C also guarantees that a (signed) short can store values between -32767 and +32767 (inclusive), which implies that it has at least 15 value bits (plus one sign bit).

    • (Score: 3, Interesting) by RamiK on Wednesday March 16 2016, @03:04PM

      by RamiK (1813) on Wednesday March 16 2016, @03:04PM (#319045)

      Nah. Plenty of legacy x86 software to make the descent slowly stretch over a decade or more. Besides, it's not all about the tech. They could sign, IBM style, government contracts keeping them in the green for decades to come.

      What Intel should be worried about is all the mainlining efforts by Asian fabless houses done in recent months in advance of production. If they can ship a 2.5GHz SoC with a PCI-e bus to market and have day0 linux support, people will slot an AMD dedicated GPU in there and call it their workstation. That will be the beginning of the end.

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      • (Score: 2) by bitstream on Wednesday March 16 2016, @03:29PM

        by bitstream (6144) on Wednesday March 16 2016, @03:29PM (#319053) Journal

        Even worse, if users can slot in another "slow" CPU and still get the same instructions per second/dollar by clever software architecture the advantage of that really fast CPU will diminish. And as the clock rate seems to level out at 4.7 GHz the competition is likely to get there to (4.0 GHz for Intel).

        The economy for new fast CPUs depend on parallelization being inefficient or impossible for the use cases. Otherwise users may just add CPUs as their processing needs change.

        • (Score: 2) by RamiK on Wednesday March 16 2016, @07:41PM

          by RamiK (1813) on Wednesday March 16 2016, @07:41PM (#319161)

          Well, what you're describing is a disruptive change in the server room that assumes inherently sequential algorithms can be circumvented in many real world scenarios without bus issues. I'm pretty sure that's not going to happen soon.
          But, what I was describing is withing the capabilities of existing designs like MediaTek's Helio X20 that's likely being fabricated by TSMC in 16nm as we speak...

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          • (Score: 2) by bitstream on Wednesday March 16 2016, @08:07PM

            by bitstream (6144) on Wednesday March 16 2016, @08:07PM (#319185) Journal

            Another solution is to solve problems with non-sequential algorithms. Ie to send a letter, instead of hiring the fastest runner you can buy for money. You send it by radio..

            • (Score: 2) by RamiK on Wednesday March 16 2016, @09:48PM

              by RamiK (1813) on Wednesday March 16 2016, @09:48PM (#319251)

              Wait, at least some relevant tasks outside academia are inherently sequential... No? It's true that 5 years ago when we didn't have parallel html parsers and concurrent image\video decoding and decompression built into our browsers, this statement carried more weight. But surely, it's still true for some server loads? Sometimes, you just can't get away from seq2seq in real life... No?

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              • (Score: 2) by bitstream on Wednesday March 16 2016, @10:20PM

                by bitstream (6144) on Wednesday March 16 2016, @10:20PM (#319268) Journal

                html parsing will likely to some extent by strictly sequential but audio, image and video compression is easy to parallelize.

                I wonder when the next 10x CPU instructions/seconds jump will happen.

    • (Score: 2) by takyon on Wednesday March 16 2016, @06:20PM

      by takyon (881) <{takyon} {at} {soylentnews.org}> on Wednesday March 16 2016, @06:20PM (#319104) Journal

      I don't know about that. They've been far ahead in process node, even with the 10nm Cannonlake delay. The fact that ARM and TSMC won't be able to use EUV in time for 7nm is very interesting, since it was assumed that would be the node where EUV would need to be deployed. It's a little shocking when you think about it. It was supposed to be available years ago, but if this information is correct, it will only be used for 5nm, 3nm, 2nm, 1nm, 0.5nm (whichever of these are possible, 0.5nm is in single atom territory).

      Intel's big problem is still ARM and Apple dominance in mobile CPUs. Even though smartphone and tablet chip growth is slowing, that's a huge market where Intel is just sputtering (tied to the success of Surface of all things). ARM isn't in many desktops or non-tablet laptops, but a trend towards laptop/desktop docks for smartphones could reverse that. Like what the Ubuntu Edge was supposed to do.

      Intel is doing well in servers/HPC. Nobody ever got fired for choosing Xeon, and Xeon Phi is successfully fighting off GPUs to be included as coprocessors in supercomputers. ARM success in hPC is very uncertain, especially if it is tied to the plans of companies like... AMD.

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