Tom's Hardware reports on a crude method that may enable the production of vertical/3D NAND with more than 100 layers in the future:
Today's 3D NAND weighs in at 32 to 48 layers, but increasing the density beyond 100 layers appears to be an impossible challenge due to the limitations of high-aspect ratio etch tools, which etch the holes in the NAND (1.8 billion for Samsung 48-layer NAND). Today's tools have 30:1 to 40:1 aspect ratios for 32- and 48-layer NAND, respectively, but creating 64-layer NAND will require an aspect ratio of 60:1 to 70:1. The only problem? There are no tools that can achieve that aspect ratio.
Several NAND vendors are reportedly developing a new "string-stacking" method that will merely stack the 3D NAND devices on top of each other. For instance, three 48-layer stacks will be stacked upon each other to create a 144-layer chip. String stacking may allow for scaling up to 300 layers, but the challenge will be how to link the stacks and produce it in a cost-effective manner. Unfortunately, the NAND fabs have not even mastered that for standard 3D NAND as of yet.
In other NAND news, there may be a shortage of 3D NAND, indicated by Samsung using 16nm 2D TLC NAND in its new 750 EVO SSDs.
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The wide adoption of 3D/vertical NAND with increased feature sizes and endurance will apparently lead to the introduction of low-cost QLC (4 bits per cell) NAND. 3D NAND's increased flash cell size and overprovisioning will counteract the reduction in endurance caused by moving from 3 to 4 bits per cell:
We covered the TSV [Through Silicon Vias] notion here and now take a look at quadruple level cell (QLC) flash technology. Toshiba will present on this and TSVs in a keynote session at the August 6-9 Flash Memory Summit in Santa Clara. The session abstract notes: "New technologies such as QLC (Quadruple Level Cell) BiCS FLASH offer high density, low-cost solutions, while TSV (Through Silicon Via) NAND offers high performance with significant power reduction."
To recap, BiCS stands for Bit Cost Scalable and is Toshiba and flash foundry partner WDC's approach to 3D NAND, the layering of ordinary or planer (2D) NAND chips atop each other. We have 48-layer cells in production and 64-layer ones coming with 96-layer and even 128-layer chips in prospect. Progress beyond 64-layers has problems due to the difficulties in etching holes through the layers and so the TSV idea is to have two layers of layering: two 64-layer chips one on top of the other, with holes through them both, TSVs, for wiring to hold them together and carry out cell activity functions as well.
[...] Back in March, Jeff Ohshima, a Toshiba executive, presented on TSVs and QLC flash at the Non-Volatile Memory Workshop and suggested 88TB QLC 3D NAND SSDs with a 500 write cycle life could be put into production. The Flash Memory Summit keynote could add more colour to this.
Related:
Toshiba and SanDisk Announce 48-Layer 256 Gb 3D NAND
Toshiba Brings Through-Silicon Vias to NAND Flash
Western Digital, SanDisk, and the NAND Market
"String-Stacking" Being Developed to Enable 3D NAND With More Than 100 Layers (NAND devices with 64 layers and above will be difficult to create, so stacking 48-layer devices will be used to increase density)
A number of companies have made announcements related to 64-layer 3D NAND production and products at Computex 2017:
64-layer NAND, and subsequently products with the technology, will make the largest splash at Computex 2017 this week. Toshiba, Western Digital, and SanDisk have product announcements in queue, with others set to follow. Toshiba already released some information about the technology at Dell World, so the other shoe has to drop from manufacturing partner WD. This is the moment many of us have waited for.
In short, Toshiba/WD are supposed to take us out of the NAND recession by delivering third-generation 3D NAND called BiCS FLASH.
BiCS FLASH may gain praise for reducing the strain on NAND supply, but our readers will be left behind for several quarters. SanDisk has said for years that the future focus will be on 3-bit per cell NAND (or TLC). That philosophy carried over to infect Western Digital after the SanDisk acquisition. No one talks about BiCS MLC for use in the client space, even though 3D TLC is unproven technology for high-performance products (outside of Samsung).
Intel and Micron's jointly-developed 3D QLC (4 bits per cell) NAND memory is featured in a new Micron enterprise SSD, the 5210 ION. The drive will have a capacity of 1.92 TB, 3.84 TB, or 7.68 TB, and a write endurance of less than 1 drive write per day (possibly as low as 0.1 DWPD):
The cost reduction brought by QLC NAND is a much-awaited advance for enterprise storage. Most NAND flash manufacturers have started sampling QLC NAND within the past year, generally built on the same 64-layer 3D NAND processes that current-generation TLC NAND uses. Micron has previously shown wafers of 512Gb 64-layer QLC when announcing the addition of QLC to their roadmap, but today they are also announcing a 1Tb 64L QLC part—the first 1Tb memory chip to hit commercial availability. That 1Tb part is organized as four planes that can be processing I/O commands in parallel, compared to two planes for previous Intel/Micron NAND parts. This helps offset most of the performance loss associated with increasing per-die capacity. Thanks to the "CMOS under the array" design of Intel/Micron 3D NAND, the extra peripheral circuitry requried by doubling the number of planes doesn't add much to the overall die size.
It was initially feared that QLC write endurance would be low enough that drives would need to be treated more or less as write-once, read-many (WORM) devices, requiring careful handling on the software side. With multiple manufacturers now rating their QLC NAND for around 1k P/E cycles, it is clear that QLC-based SSDs aren't too fragile and can handle many existing workloads without needing major software changes to reduce writes.
Micron is primarily marketing the 5210 ION SSDs as replacement for hard drives, rather than replacements for any existing tier of enterprise SSD products. In this role, the 5210 ION will have clear advantages in density (with 2-8TB per 2.5" drive) and performance. QLC NAND only provides incremental improvements to cost, so the 5210 ION won't be matching 7200RPM hard drives for price per GB, but 10k RPM drives will probably be feeling the pressure, especially from TCO calculations that take into account the power efficiency advantages of SSDs.
The next generation of Intel/Micron 3D NAND will have 96 layers, potentially using string-stacking to combine two 48-layer dies. After that, Intel and Micron will go their separate ways.
At present Micron is ramping up production of its 64-layer 3D TLC NAND memory (2nd Gen 3D NAND) and last quarter it achieved production output crossover with other types of NAND the company manufactures. This is particularly good news for Micron because 64-layer 3D NAND devices are significantly more cost-efficient in terms of cost per bit compared to 32-layer 3D NAND memory, which allows Micron to earn more. In fact, 64-layer 3D NAND enabled Micron to launch two major products. First, the company released its 2.5-inch SATA 5200 ECO SSDs with up to 7.68 TB capacity in January targeting mainstream servers. Second, 64-layer 3D QLC memory enabled Micron to compete for nearline storage segment with its 5210 ION drives launched back in May.
Earlier this month we reported that at least two developers of SSD controllers have qualified Micron's 96-layer 3D TLC NAND memory for SSDs. During the conference call, Micron confirmed that it was on track to ship its 3rd Gen 3D NAND in volumes for commercial products in the second half of calendar 2018. It is not clear whether the initial batches of such memory will be used for various removable storage solutions (memory cards, USB flash drives, etc.) as it happens usually, but it is evident that Micron's 96-layer 3D NAND is making a good progress with designers of SSD controllers. Maxio Technology intends to use Micron's 3D TLC B27A memory for inexpensive drives based on its MAS0902A-B2C DRAM-less controller, whereas Silicon Motion is so confident of this memory that it has qualified it with its top-of-the-range SM2262EN controller for high-performance SSDs.
[...] While sales of Micron's SSDs are growing (and currently account for 50% of Micron's storage business revenue, or $507 million) and the company continues to shift to high-value specialized NAND products from selling raw NAND chips, shipments of 3D XPoint are below expectations. According to Micron, it sold "very little" 3D XPoint memory to its unnamed parter (almost certainly Intel) during its Q3 FY2018.
Micron's 4th-generation 3D NAND could have up to 128 layers.
Related: "String-Stacking" Being Developed to Enable 3D NAND With More Than 100 Layers
64-Layer 3D NAND at Computex
SK Hynix Developing 96 and 128-Layer TLC 3D NAND
Intel and Micron Boost 3D XPoint Production
Micron Launches First QLC NAND SSD
SK Hynix Starts Production of 128-Layer 4D NAND, 176-Layer Being Developed
SK Hynix has announced it has finished development of its 128-layer 1 terabit 3D TLC NAND flash. The new memory features the company's charge trap flash (CTF) design, along with the peripheral under cells (PUC) architecture that the company calls '4D' NAND, announced some time ago. The new 128-layer TLC NAND flash devices will ship to interested parties in the second half of this year, and SK Hynix intends to offer products based on the new chips in 2020.
[...] In the first half of next year SK Hynix promises to roll out its UFS 3.1 storage products based on the new 1 Tb devices. The company plans to offer 1 TB UFS 3.1 chips that will consume up to 20% less [power] when compared to similar products that use 512 Gb ICs.
[...] String stacking technology, as well as the multi-stacked design, will enable SK Hynix to keep increasing the number of layers. SK Hynix says that it is currently developing 176-layer 4D NAND flash, but does not disclose when it is expected to become available.
Previously: "String-Stacking" Being Developed to Enable 3D NAND With More Than 100 Layers
SK Hynix Developing 96 and 128-Layer TLC 3D NAND
Related: Expect 20-30% Cheaper NAND in Late 2018
Micron: 96-Layer 3D NAND Coming, 3D XPoint Sales Disappoint
Western Digital Samples 96-Layer 3D QLC NAND with 1.33 Tb Per Die
Samsung Shares Plans for 96-Layer TLC NAND, QLC NAND, and 2nd-Generation "Z-NAND"
(Score: 2) by butthurt on Saturday May 28 2016, @07:06PM
Would it be feasible to put blobs of solder on the chips, stack, and heat them so connections are formed?
(Score: 1, Insightful) by Anonymous Coward on Sunday May 29 2016, @04:25AM
I've wondered the same thing, but then I saw, "(1.8 billion for Samsung 48-layer NAND)". Even if it only needs 1% of that many connections, that's a lotta tiny solder balls.