An article at Hackerboards is reporting the announcement that fabless semiconductor company SiFive has announced the first embedded SoCs based on the open source RISC-V platform
A VC-backed startup closely associated with the RISC-V project announced the first system-on-chip implementations of the open source RISC-V processor platform. At the RISC-V 4thWorkshop at MIT this week, SiFive announced two embedded SoC families. The Freedom Unleashed family debuts with a 28nm fabricated, Freedom U500 SoC with up to eight 1.6GHz cores that runs Linux, aimed at machine learning, storage, and networking applications. The MCU-like Freedom Everywhere family for Internet of Things starts with a 180nm Freedom E300 model that runs FreeRTOS.
Like RISC-V, both designs are fully open source, but the company also plans to sell finished SoCs with the help of fabrication partner TSMC. The platform will "reverse the industry's prohibitively rising licensing, design and implementation costs," says SiFive.
Although the SiFive announcement talks about the final SoC implementation currently only targets based on standard FPGA based development platforms appear to be available.
This earlier SN article contains more information on the RiscV project and the development of an open Instruction Set Architecture.
Related Stories
The RISC-V project ran the first RISC-V workshop last week, and the content from the workshop is being brought online.
Currently the slide packs are available, with videos to follow. From the blog posting
The videos from the workshop are still being prepared for distribution, but the slides from the talks are now available online at http://riscv.org/workshop-jan2015.html. [Ed Comment: URL intermittent] They represent the most up-to-date information on the Berkeley RISC-V tools and infrastructure.
The RISC-V Project aims to develop an open Instruction Set Architecture (ISA) under a BSD License; from the project homepage:
Our intent is to provide a long-lived open ISA with significant infrastructure support, including documentation, compiler tool chains, operating system ports, reference software simulators, cycle-accurate FPGA emulators, high-performance FPGA computers, efficient ASIC implementations of various target platform designs, configurable processor generators, architecture test suites, and teaching materials. Initial versions of all of these have been developed or are under active development. This material is to be made available under open-source licenses.
The motivation for the project is summarised in The Case for RISC-V (PDF Download) .
Qualcomm Invests in RISC-V Startup SiFive
Investors are zeroing in on the open standard RISC-V instruction set architecture and the processor intellectual property being developed by a batch of high-flying chip startups.
Last fall, Esperanto Technologies announced a $58 million funding round. The chip IP vendor is incorporating more than 1,000 RISC-V cores onto a single 7-nm chip. Data storage specialist Western Digital is an early investor in Esperanto, Mountain View, Calif.
This week, another RISC-V startup, SiFive, announced a $65.4 million funding round that included new investor Qualcomm Ventures. SiFive, San Mateo, Calif., has so far raised more than $125 million, and is seen as a challenger to chip IP leader Arm.
Observers note that wireless modem leader Qualcomm is among Arm's biggest customers, making its investment in SiFive intriguing. Also participating in the Series D round were existing investors Chengwei Capital of Shanghai along with Sutter Hill Ventures and Spark Capital. Intel Capital and Western Digital also were early investors.
Also at EE Times.
See also: SiFive Acquires USB 2.0 and 3.x IP Portfolio to Strengthen RISC-V SoCs
Previously: RISC-V Projects to Collaborate
SiFive and UltraSoC Partner to Accelerate RISC-V Development Through DesignShare
SiFive Introduces RISC-V Linux-Capable Multicore Processor
SiFive HiFive Unleashed Not as Open as Previously Thought
Linux Foundation and RISC-V Proponents Launch CHIPS Alliance
Separately, a handful of RISC-V proponents launched the CHIPS Alliance, a project of the Linux Foundation to develop a broad set of open-source IP blocks and tools for the instruction set architecture. Initial members include Esperanto, Google, SiFive, and Western Digital. CHIPS stands for Common Hardware for Interfaces, Processors, and Systems.
Esperanto Technologies and SiFive look like the names to watch.
Related: First Open Source RISC-V Implementations Become Available
Western Digital Unveils RISC-V Controller Design
Raspberry Pi Foundation Announces RISC-V Foundation Membership
Western Digital Publishes RISC-V "SweRV" Core Design Under Apache 2.0 License
(Score: 2) by jmorris on Friday July 15 2016, @05:49PM
This looks like everything we have been crying out for. A CPU that is fast enough to be usable with no evil bits and no secret parts. All they have to do now is turn the press release into shipping silicon.
(Score: 2, Disagree) by RamiK on Friday July 15 2016, @06:12PM
It IS a shipping product... Two in fact:
Xilinx Virtex-7 VC707 FPGA Dev Kit for $3,495 [xilinx.com]
Digilent Arty Board Artix-7 FPGA Development Board for $99 [digilentinc.com]
And to add something that isn't in the press release or summary: http://www.lowrisc.org/blog/2016/07/notes-from-the-fourth-risc-v-workshop/ [lowrisc.org]
compiling...
(Score: 4, Interesting) by jmorris on Friday July 15 2016, @06:34PM
No, those are FPGA boards to emulate the eventual product. You buy those to begin development of software now that will target the promised silicon to come. Any FPGA based system is going to be expensive, slow and consume vast amounts of power. There are a ton of soft cpu cores running on various FPGA chips, that is not newsworthy. What is newsworthy is the announcement of an entirely open source SoC where somebody is spending the money to take one of the free designs and put it on real silicon along with enough I/O to build a real viable personal computer that is free of blobs, drm and undocumented hardware.
(Score: 4, Insightful) by RamiK on Friday July 15 2016, @07:57PM
FPGA boards to emulate the eventual product
Since when FPGA was "emulation"? It's real switching. If their product is an open design, then the availability of FPGA boards is shipped products.
It's like saying a FOSS repository hosting a working code-base isn't considered a release since no one printed it in a CD and sold it...
But to give a more related example, in the early days of HDMI decryption, the first products sold were FPGA boards. They weren't sold as prototypes or as an extra feature. But as decryption boards. Just a little while ago, there was talks about SoCs that would come with some FPGA to reduce licensing costs from the OEMs and move them as after-market upgrade options that can even be upgraded over time.
A few years ago I would side with you. But now that there are products that ship as FPGA...
compiling...
(Score: 2) by Scruffy Beard 2 on Friday July 15 2016, @10:50PM
The problem is most FPGAs are all proprietary. Not more proprietary than the average ASIC, but still.
(Score: 2) by RamiK on Tuesday July 26 2016, @07:25PM
Here you go: https://www.phoronix.com/scan.php?page=news_item&px=NVIDIA-RISC-V-Next-Gen-Falcon [phoronix.com]
compiling...
(Score: 2) by linuxrocks123 on Friday July 15 2016, @07:21PM
There's also this, for people looking for that: https://www.raptorengineering.com/TALOS/prerelease.php [raptorengineering.com]
(Score: 2) by hendrikboom on Friday July 15 2016, @08:54PM
That Talos system is still too expensive.
(Score: 0) by Anonymous Coward on Friday July 15 2016, @08:19PM
But also a more rapid release cycle, and focus on a new open source motherboard standard.
Given how cheap PCI is for instance, and assuming the patents have already run out (and other issues like copyrighted slot designs aren't a problem...) we could run a series of PCI busses connected to an open source high speed IO-bus to allow more slots with full bandwidth (while avoiding the patents still on PCIe) Then if necessary have PCI->PCIe converters for running newer IO boards (there are still PCI -> PCIe adapters available for china for 25 bucks a slot. If you only need them for an occasional video card, or storage controller, this should be acceptable for 'security over price' system without breaking the bank.)
Should PCI be out, then the two options I see are using SBUS (1 dollar royalty free licensing cost from the SPARC Consortium), possibly with a backwards compatible series of improved busses (IOMMU support by default as a bonus!) Or creating a new bus with new (incompatible) connectors to provide an open source IO standard for the future (this is most ideal from a patent/future proofing point of view, but also dangerous since it affects the cost and availability of IO devices.) A third possibility I just thought of would be using a serial bus similiar, but unrelated to USB3/Firewire for all IO (With a seperate power connector standard for high power devices) and simply adding more channels to the SOC/Motherboard chipset. Assuming you could avoid the patent minefield this would give the most opportunities for connecting patented devices, but also likely the slowest speed, by putting IO devices off the equivalent of USB3 switches outside of the board/case, and allowing any patent encumbered components to be isolated off the motherboard, connected via patent free technologies up to whatever conversion device was used. Getting the cost of those conversion boards to less than the price of a motherboard would be a major priority, but if done, could allow open source hardware to advance with its own standards, while still benefitting from newer technology provided on proprietary but industry standard bus architectures.
One suggestion I have if somebody takes this on: Ensure the bus has a scalable memory aperture for 16,32,64,128, and possible 256 bit addresses, As the Xeon Phi and now AMD Hybrid GPUs should indicate, having the ability to provide larger IO windows than you can imagine possible is important to ensuring your motherboards can still use newer IO devices, even if the standard itself doesn't really change (64 bit PCI BAR has been around since the 90s, but nothing(?) implemented it until recent Intel hardware, making it easy for Intel to break the Xeon Phi on non-Intel hardware. And AMD has continued dragging its feet on getting support into non-APU hardware.)
Whether it is RISC-V or another chip, we're rapidly running out of time to fight for control of our computer hardware. Every major designer and manufacturer is using signed firmware and greater than 'hardware ring' privileges to access features of the hardware that compromise guarantees of system security for the end user. If we don't fight it off now, everything, including open source hardware designs will become suspect (if they are not already.) If that comes to pass the only path to recovery would be rebooting the industry from hand designed hardware and compilers (again!) to ensure no backdoors were inserted for either hardware or software. And I don't know about you, but I doubt the current collection of internatonal governments would legally allow us to bootstrap unsigned hardware by the point the next opportunity at 'open source computing revolution' happens, if not today.
Sorry if I come off as crazy. But it is my sincere belief we are just a step away from being enslaved with technology in the same way certain groups were enslaved and persecuted based on their skin color, ethnic origins, or religious beliefs. The only difference being, while there were places to run for them, if they ran far enough, there will be no where for us to run because the collective world order is all moving towards the same set of evil laws, even if they all only want to enforce it domestically.
(Score: 2) by Scruffy Beard 2 on Friday July 15 2016, @10:55PM
A laptop or netbook based on the Embedded Open Modular Architecture/EOMA-68 [elinux.org] would be sweet.
Bonus points if it uses a transflective display for use in full sunlight.
(Score: 0) by Anonymous Coward on Saturday July 16 2016, @04:00PM
too expensive and the selection of off-module IO leaves a lot to be desired.
Honestly, given the CPU selection, it isn't any better than just buying a cheap chinese android netbook and reflashing it with a proper linux distro.
EOMA is probably good for certain embedded/industrial applications, but doesn't really make a good general purpose computer module.
(Score: 2) by wonkey_monkey on Friday July 15 2016, @08:36PM
A CPU that is fast enough to be usable with no evil bits
Apart from the evil bit [wikipedia.org].
systemd is Roko's Basilisk
(Score: 0) by Anonymous Coward on Friday July 15 2016, @11:49PM
"This looks like everything we have been crying out for. A CPU...." yes, but a GPU is needed to go along with it, in today's world.
(Score: 0) by Anonymous Coward on Saturday July 16 2016, @04:03PM
You could just have a couple of them with massive simd/mimd fpu arrays handling the gpu features as well. May or may not be as energy efficient, but could certainly be used to bring up a minimum level of performance even using mesa's software implementation.
(Score: 2) by TheRaven on Sunday July 17 2016, @12:01PM
sudo mod me up
(Score: 2) by Gravis on Friday July 15 2016, @10:21PM
I would love to see a heavyweight class RISC-V CPU so that real libre desktop computers could be constructed. This is a good start and could be used to construct a libre smartphone or a Chromebook-esque laptop.