The wide adoption of 3D/vertical NAND with increased feature sizes and endurance will apparently lead to the introduction of low-cost QLC (4 bits per cell) NAND. 3D NAND's increased flash cell size and overprovisioning will counteract the reduction in endurance caused by moving from 3 to 4 bits per cell:
We covered the TSV [Through Silicon Vias] notion here and now take a look at quadruple level cell (QLC) flash technology. Toshiba will present on this and TSVs in a keynote session at the August 6-9 Flash Memory Summit in Santa Clara. The session abstract notes: "New technologies such as QLC (Quadruple Level Cell) BiCS FLASH offer high density, low-cost solutions, while TSV (Through Silicon Via) NAND offers high performance with significant power reduction."
To recap, BiCS stands for Bit Cost Scalable and is Toshiba and flash foundry partner WDC's approach to 3D NAND, the layering of ordinary or planer (2D) NAND chips atop each other. We have 48-layer cells in production and 64-layer ones coming with 96-layer and even 128-layer chips in prospect. Progress beyond 64-layers has problems due to the difficulties in etching holes through the layers and so the TSV idea is to have two layers of layering: two 64-layer chips one on top of the other, with holes through them both, TSVs, for wiring to hold them together and carry out cell activity functions as well.
[...] Back in March, Jeff Ohshima, a Toshiba executive, presented on TSVs and QLC flash at the Non-Volatile Memory Workshop and suggested 88TB QLC 3D NAND SSDs with a 500 write cycle life could be put into production. The Flash Memory Summit keynote could add more colour to this.
Related:
Toshiba and SanDisk Announce 48-Layer 256 Gb 3D NAND
Toshiba Brings Through-Silicon Vias to NAND Flash
Western Digital, SanDisk, and the NAND Market
"String-Stacking" Being Developed to Enable 3D NAND With More Than 100 Layers (NAND devices with 64 layers and above will be difficult to create, so stacking 48-layer devices will be used to increase density)
Related Stories
Toshiba and SanDisk have announced the development of a new 3D NAND product (called V-NAND by Samsung). It uses 48 layers of triple-level cell (TLC) NAND to store 256 Gb (32 GB) in a single die. It is expected to sample in September, and appear in solid-state drives and other products in the second half of 2016. However, the two companies will face plenty of competition. From Anandtech:
The new 3D NAND will face experienced competition from Samsung who are currently shipping 32-layer 3D NAND in capacities up to 128Gb for both MLC and TLC configurations. Samsung has also announced its third generation V-NAND which should be starting mass production in the latter half of this year. Meanwhile, Intel and Micron have stated that their 32-layer 3D NAND will be in mass production by the fourth quarter of this year in the form of a 256Gb MLC die and a 384Gb TLC die. SK Hynix is to begin mass production of a 36-layer 128Gb MLC die during the third quarter and is working toward a 48-layer TLC that will be available in 2016.
All of the major flash manufacturers have now publicized their plans for introducing 3D NAND. Planar NAND won't be disappearing overnight or even in a year, as it takes a lot of time and money to convert a fab to a new process. But from here on out, we can expect all the most interesting news about NAND flash memory to be about 3D.
Toshiba has showed off a NAND flash device using through-silicon vias (TSVs) to stack 16 NAND dies, a technology it announced earlier this month. From Tom's Hardware:
TSV technology removed the wire bonding from the edges of the die. Instead, the signal is passed through the entire stack vertically. Vertical NAND, often referred to as V-NAND or 3D NAND, differs from TSV, though. Nothing leads us to believe that the two technologies can't work together, but at this time we are unaware of any designs that merge the two technologies.
[...] Toshiba's partners are excited about this product for two reasons: The first is performance. PMC Sierra makes very high-performing NVMe SSDs that move the bottleneck from the PCIe interface to the flash itself. The Princeton controller uses 32 channels to address a large number of flash die and is a very expensive controller to manufacture. If the company is able to reach the same performance level with just 16 channels, the overall cost will drop. The capacity can remain the same because TSV allows Toshiba to stack twice the number of die in each package.
Performance is only one aspect of the overall datacenter equation, though. The upfront costs are minimal compared to the long term costs due to power consumption. PMC Sierra demonstrated a very wide gap in power efficiency between non-TSV Toggle mode flash and new TSV Toggle mode flash.
The use of TSV could help scale NAND capacity in the vertical dimension even further.
Following Western Digital's purchase of SanDisk, now is a good time to look to the future of the disk and NAND flash storage industries:
Stifel [Managing Director] Aaron Rakers has taken a deep dive look at the SanDisk technology Western Digital is aiming to buy, and his report brings out cost-savings derived from HGST escaping payment of an Intel tax, 3D NAND timescales, and possibilities for future planar NAND node shrinks.
[...] Rakers points out that "the write attributes of shingled magnetic recording (SMR) technologies requires the usage of non-volatile persistent memory (NAND) in order to optimise write performance (e.g., transition tables)." HGST's 10TB HelioSeal disk drives use SMR and, if Rakers is right, will need to be hybrid flash/disk drives with flash being used for SMR block rewrite operations. SanDisk can supply the flash chips for this.
Unexpectedly, there could be another 2D planar NAND node shrink to below 15nm. Rakers writes: "We believe that SanDisk continues to prepare for the possibility of another planar node shrink (i.e. to 10/12nm); whether the company actually commences a subsequent planar node shrink depends on the cost effectiveness ramp of SanDisk's 3D NAND ... demand for various types of NAND in different use cases, and the difference in investment required to continue to produce 15nm TLC, convert to 3D NAND, build greenfield 3D NAND or further shrink planar."
[...] Raker's financial modelling of WD's post-SanDisk acquisition SSD costs indicates that building products using vertically-integrated SanDisk technology for enterprise SAS SSDs could save WD substantial amounts of money. He thinks that 80-85 per cent of the enterprise SSD bill-of-material (BOM) cost is for NAND flash. Modelling with an average 900GB SSD he reckons WD could be paying Intel as much as $0.60/GB for flash chips. It would save as much as 52 per cent of this by using SanDisk chips.
[More after the break.]
Tom's Hardware reports on a crude method that may enable the production of vertical/3D NAND with more than 100 layers in the future:
Today's 3D NAND weighs in at 32 to 48 layers, but increasing the density beyond 100 layers appears to be an impossible challenge due to the limitations of high-aspect ratio etch tools, which etch the holes in the NAND (1.8 billion for Samsung 48-layer NAND). Today's tools have 30:1 to 40:1 aspect ratios for 32- and 48-layer NAND, respectively, but creating 64-layer NAND will require an aspect ratio of 60:1 to 70:1. The only problem? There are no tools that can achieve that aspect ratio.
Several NAND vendors are reportedly developing a new "string-stacking" method that will merely stack the 3D NAND devices on top of each other. For instance, three 48-layer stacks will be stacked upon each other to create a 144-layer chip. String stacking may allow for scaling up to 300 layers, but the challenge will be how to link the stacks and produce it in a cost-effective manner. Unfortunately, the NAND fabs have not even mastered that for standard 3D NAND as of yet.
In other NAND news, there may be a shortage of 3D NAND, indicated by Samsung using 16nm 2D TLC NAND in its new 750 EVO SSDs.
Samsung recently announced its fourth generation of 3D/vertical NAND, with 64 layers and a capacity of 512Gb (64GB) per die. Now SK Hynix is announcing its plans for 512 Gb V-NAND dies with 72 layers:
Later this year SK Hynix intends to start volume production of 72-layer 3D TLC NAND (3D-V4) memory and this is where things start to get interesting. Initially, SK Hynix intends to produce 256 Gb 3D TLC ICs and these are going to be available already in Q2 2017, according to the company's product catalog. Later on, sometimes in Q4, the company plans to introduce 512 Gb 3D TLC ICs (64 GB), which will help it to significantly increase capacities of SSDs and other devices featuring NAND flash.
What is important about SK Hynix's fourth-gen 3D NAND is that it will feature block size of 13.5 MB, which will increase the performance of such ICs compared to 3D-V3 and 3D-V2 that have a block size of 9 MB. At this point, we do not know whether SK Hynix intends to increase interface speed of its 512 Gb 3D-V4 ICs to compensate lower parallelism in lower-capacity SSDs, like Samsung did with its high-capacity 64-layer 3D V-NAND chips. What we do know is that SK Hynix's catalog already includes NAND multi-chip packages of 8192 Gb capacity (1 TB) that will enable high-capacity SSDs in smaller form-factors (e.g., [2 TB] single-sided M.2). Meanwhile, 64 GB NAND flash chips may force SK Hynix and its partners to abandon low-capacity SSDs (i.e., 120/128 GB) unless there is sufficient demand.
The article also talks about the company's plans for 18nm DRAM and fabrication facility expansion.
Related: Toshiba and SanDisk Announce 48-Layer 256 Gb 3D NAND
Toshiba Teasing QLC 3D NAND and TSV for More Layers
Toshiba continues to look for a buyer for its memory business:
South Korea's SK Hynix Inc has entered the running for a stake in Toshiba Corp's memory chip business, seeing an opportunity to gain on rivals in the booming NAND market, a person familiar with the matter said on Tuesday.
The world's No. 2 memory chip maker had submitted an initial bid, although the size of the stake it wanted to acquire had not been decided, the source told Reuters, requesting anonymity as they were not authorized to speak publicly on the deal.
[...] Toshiba aims to raise more than 200 billion yen ($1.7 billion) from the less-than 20 percent stake in its memory business, sources have said. The sale is part of a broader sell-off to cover multi-billion dollar writedowns stemming from its U.S. nuclear power unit.
Previously: Toshiba Teasing QLC 3D NAND and TSV for More Layers
Toshiba Envisions a 100 TB QLC SSD in the "Near Future"
Toshiba Considers NAND Business Split; Samsung Delays Release of 4 TB SSDs
A joint bid by the U.S. company Broadcom Limited and the Japanese government may keep Toshiba's chip business out of the hands of China or South Korea:
A Japanese government-backed fund and policy bank are considering a joint bid with Broadcom Ltd for Toshiba Corp's semiconductor business, a move that would vault the U.S. chipmaker into the lead to buy the prized unit, the Asahi newspaper said on Wednesday.
A bid by Innovation Network Corp of Japan and the Development Bank of Japan with Broadcom would appear to be aimed at preventing Toshiba's chip technology from going to rivals in China or South Korea, the Asahi said, citing an unidentified source.
INCJ Chairman Toshiyuki Shiga said on Tuesday the fund was looking at the chip auction although it had not participated in the first round of bidding. People familiar with the matter have told Reuters INCJ might invest in the business as a minority partner - a move that would help the government prevent a sale to bidders it deems risky to national security.
Previously: Toshiba and SanDisk Announce 48-Layer 256 Gb 3D NAND
Toshiba in Trouble
Toshiba Teasing QLC 3D NAND and TSV for More Layers
Toshiba Envisions a 100 TB QLC SSD in the "Near Future"
Toshiba Considers NAND Business Split; Samsung Delays Release of 4 TB SSDs (WD is a bidder)
SK Hynix to Bid for Toshiba's Memory Business
Toshiba Nuked Half its Assets
Huge Nuclear Cost Overruns Push Toshiba's Westinghouse Into Bankruptcy
Toshiba Warns That its Survival is at Risk
A number of companies have made announcements related to 64-layer 3D NAND production and products at Computex 2017:
64-layer NAND, and subsequently products with the technology, will make the largest splash at Computex 2017 this week. Toshiba, Western Digital, and SanDisk have product announcements in queue, with others set to follow. Toshiba already released some information about the technology at Dell World, so the other shoe has to drop from manufacturing partner WD. This is the moment many of us have waited for.
In short, Toshiba/WD are supposed to take us out of the NAND recession by delivering third-generation 3D NAND called BiCS FLASH.
BiCS FLASH may gain praise for reducing the strain on NAND supply, but our readers will be left behind for several quarters. SanDisk has said for years that the future focus will be on 3-bit per cell NAND (or TLC). That philosophy carried over to infect Western Digital after the SanDisk acquisition. No one talks about BiCS MLC for use in the client space, even though 3D TLC is unproven technology for high-performance products (outside of Samsung).
SK Hynix is currently developing 96-layer and 128-layer 3D NAND with 3 bits per cell, but may be skipping quad-level cell 3D NAND for some time:
The 64-layer 3D NAND about to land from Micron and Toshiba certainly sounds impressive, but it pales in comparison to what Sk Hynix is working on for future release. The company is developing 96-layer and 128-layer 3D NAND flash. The new flash won't be available for a few years, but that makes it no less exciting. We have yet to see 72-layer 3D from Sk Hynix in our lab, but it will begin shipping soon in the PC401 using 256Gbit TLC die, according to the UNH-IOL list of tested products.
The information we found about the successor to 256Gbit 72-layer 3D TLC shows 96 layers with 512Gbit die capacity. The follow up to that is a massive 1Tbit die from 128-layer TLC from the other South Korean SSD manufacturer with full vertical integration.
Toshiba (or whichever company acquires Toshiba's memory division) may be more likely to introduce QLC 3D NAND.
Previously:
SK Hynix Plans 72-Layer 512 Gb NAND for Late 2017
64-Layer 3D NAND at Computex
Both Toshiba (or whomever ends up buying Toshiba's memory fabrication assets) and Western Digital (WD) have both recently announced plans to produce 3D QLC (four bits per cell) NAND:
Western Digital's SanDisk subsidiary and Toshiba have a long history of jointly developing and manufacturing NAND flash memory. While that relationship has been strained by Toshiba's recent financial troubles and attempts to sell of their share of the memory business, the companies are continuing to develop new flash memory technology and are still taking turns making new announcements. In recent months both companies have started sampling SSDs using their 64-layer BiCS3 TLC 3D NAND and have announced that their next generation BiCS4 3D NAND will be a 96-layer design.
Yesterday Western Digital made a small announcement about their other main strategy for increasing density: storing more bits per memory cell. Western Digital will introduce four bit per cell QLC parts built on their 64-layer BiCS3 process, with a capacity of 768Gb (96GB) per die. This is a substantial increase over the 512Gb BiCS3 TLC parts that will be hitting the market soon, and represents not only an increase in in bits stored per memory cell but an increase in the overall size of the memory array. These new 3D QLC NAND parts are clearly intended to offer the best price per GB that Western Digital can manage, but Western Digital claims performance will still be close to that of their 3D TLC NAND. Western Digital's announcement did not mention write endurance, but Toshiba's earlier announcement of 3D QLC NAND claimed endurance of 1000 program/erase cycles, far higher than industry expectations of 100-150 P/E cycles for 3D QLC and comparable to 3D TLC NAND.
Western Digital will showcase SSDs and removable flash media using QLC NAND at the Flash Memory Summit from August 8-10.
Will QLC NAND endurance become a bigger issue than it is with TLC? Will this be used primarily for high density cold storage like Facebook has asked for?
Previously: Toshiba Teasing QLC 3D NAND and TSV for More Layers
SK Hynix Developing 96 and 128-Layer TLC 3D NAND
Western Digital Announces 96-Layer 3D NAND, Including Both TLC and QLC
Toshiba's 3D QLC NAND Could Reach 1000 P/E Cycles
Toshiba Develops 512 GB and 1 TB Flash Chips Using TSV
