Western Digital has announced its intention to include 3D Resistive RAM (ReRAM) as storage class memory (SCM) in future SSDs and other products:
Without making any significant announcements this week, Western Digital indicated that it would use some of the things it has learnt while developing its BiCS 3D NAND to produce its ReRAM chips. The company claims that its ReRAM will feature a multi-layer cross-point implementation, something it originally revealed a while ago.
Perhaps, the most important announcement regarding the 3D ReRAM by Western Digital is the claim about scale and capital efficiency of the new memory. Essentially, this could mean that the company plans to use its manufacturing capacities as well as its infrastructure (testing, packaging, etc.) in Yokkaichi, Japan, to make 3D ReRAM. Remember that SCM is at this point more expensive than NAND, hence, it makes sense to continue using the current fabs and equipment to build both types of non-volatile memory so ensure that the SCM part of the business remains profitable.
One of WD's slides projects SCM as 50% the cost per gigabyte of DRAM in 2017, declining to 5% by 2023.
Samsung introduced its fourth generation of vertical NAND, with 64 layers:
With a per-die capacity of 512Gb (64GB), Samsung can now put 1TB of TLC flash in a single package. This means most product lines will be seeing an increase in capacity at the high end of the range. Their BGA SSD products will be offering 1TB capacity even in the 11.5mm by 13mm form factor. The 16TB PM1633a SAS SSD will be eclipsed by the new 32TB PM1643. Likely to be further out, the PM1725 PCIe add-in card SSD will be succeeded by the PM1735 with a PCIe 4 x8 host interface.
Complementing the NAND update will be a new non-standard oversized M.2 form factor 32mm wide and 114mm long, compared to the typical enterprise M.2 size of 22mm by 110mm. A little extra room can go a long way, and Samsung will be using it to produce 8TB drives. These will be enterprise SSDs and Samsung showed a diagram of these enabling 256TB of flash in a 1U server. Samsung will also be producing 4TB drives in standard M.2 sizing.
In what is likely a bid to steal some thunder from 3D XPoint memory before it can ship, Samsung announced Z-NAND memory technology and a Z-SSD product based around Z-NAND and a new SSD controller. They said nothing about the operating principles of Z-NAND, but they did talk about their plans for the Z-SSD products.
Related Stories
Samsung Shares SSD Roadmap for QLC NAND And 96-layer 3D NAND
At Samsung's Tech Day event today in San Jose, the company shared their SSD roadmap for transitioning to 96-layer 3D NAND and introducing four bit per cell (QLC) NAND flash memory. Successors have been named for most of their current SSDs that use three bit per cell (TLC) NAND flash and are being updated with 96-layer 3D TLC, and new product lines using QLC NAND have been introduced.
[...] The enterprise SAS product line is not seeing any major changes to performance or available capacities, but the update from the PM1643 to the PM1643a does improve random write performance by about 20%. The largest model remains 30.72TB. The high-end enterprise NVMe drives are getting a major controller update that brings PCIe 4.0 support in addition to the NAND upgrade. This allows for much higher performance across the board, most notably with sequential read speeds reaching 8GB/s on the new PM1733 compared to 3.5GB/s on the PM1723b. The maximum available capacity has caught up to the SAS product line with the introduction of a 30.72TB model.
[...] Samsung also mentioned that in Q2 2019 they are planning to introduce a higher-performing 512Gb QLC die to complement their current 1Tb die. Samsung compared the performance of this new 512Gb die against an unspecified competitor's 1Tb QLC, claiming that Samsung's high-performance QLC will have 37% lower read latency and 45% lower program latency.
[...] The first products featuring the second generation of Samsung's low-latency Z-NAND flash memory will be the SZ1733 and SZ1735, high-end enterprise NVMe SSDs that differ primarily in the amount of overprovisioning. Samsung has announced that their second generation of Z-NAND will include a MLC version, but these drives are using the SLC version. Like the TLC-based PM1733, the new Z-NAND SSDs will also feature dual-port capability and PCIe 4.0 support. Sequential reads of up to 12GB/s are claimed, but this product line is all about random I/O, which Samsung hasn't detailed yet. Samsung demoed a 4TB model, significantly larger than the 800GB maximum for the first-generation SZ985.
Z-NAND (PDF) has lower latency than normal NAND, and could be compared to Intel and Micron's 3D XPoint.
Related: Western Digital and Samsung at the Flash Memory Summit
Samsung Announces a 128 TB SSD With QLC NAND
Samsung Announces Production of 1-4 TB Consumer 3D QLC NAND SSDs
Samsung recently announced its fourth generation of 3D/vertical NAND, with 64 layers and a capacity of 512Gb (64GB) per die. Now SK Hynix is announcing its plans for 512 Gb V-NAND dies with 72 layers:
Later this year SK Hynix intends to start volume production of 72-layer 3D TLC NAND (3D-V4) memory and this is where things start to get interesting. Initially, SK Hynix intends to produce 256 Gb 3D TLC ICs and these are going to be available already in Q2 2017, according to the company's product catalog. Later on, sometimes in Q4, the company plans to introduce 512 Gb 3D TLC ICs (64 GB), which will help it to significantly increase capacities of SSDs and other devices featuring NAND flash.
What is important about SK Hynix's fourth-gen 3D NAND is that it will feature block size of 13.5 MB, which will increase the performance of such ICs compared to 3D-V3 and 3D-V2 that have a block size of 9 MB. At this point, we do not know whether SK Hynix intends to increase interface speed of its 512 Gb 3D-V4 ICs to compensate lower parallelism in lower-capacity SSDs, like Samsung did with its high-capacity 64-layer 3D V-NAND chips. What we do know is that SK Hynix's catalog already includes NAND multi-chip packages of 8192 Gb capacity (1 TB) that will enable high-capacity SSDs in smaller form-factors (e.g., [2 TB] single-sided M.2). Meanwhile, 64 GB NAND flash chips may force SK Hynix and its partners to abandon low-capacity SSDs (i.e., 120/128 GB) unless there is sufficient demand.
The article also talks about the company's plans for 18nm DRAM and fabrication facility expansion.
Related: Toshiba and SanDisk Announce 48-Layer 256 Gb 3D NAND
Toshiba Teasing QLC 3D NAND and TSV for More Layers
Toshiba has provided more details about XL-FLASH, a high-performance version of 3D 1-bit-per-cell NAND memory:
Last year at Flash Memory Summit, Toshiba announced XL-FLASH, a specialized low-latency SLC[*] 3D NAND flash memory that is their answer to Samsung's Z-NAND (and to a lesser extent, Intel's 3D XPoint). Few details were provided at the time, but this year Toshiba is ready to give out more information, including a timeline for bringing it to market: sampling starts next month, and mass production begins next year.
The first XL-FLASH parts will use a 128Gb die, divided into 16 planes to support a much higher degree of parallelism than existing capacity-oriented 3D NAND parts. The page size will be 4kB, significantly smaller than what most 3D NAND uses, but that's not a surprise given that XL-FLASH is storing just one bit per cell rather than three or four. Toshiba's press release does not disclose the erase block size, but we expect it to be similarly smaller than what's used in high-capacity NAND designs. As for performance, Toshiba says read latency will be less than 5 microseconds, compared to about 50 µs for their 3D TLC.
Package size is 32 GB (2 dies), 64 GB (4 dies), or 128 GB (8 dies).
3D SLC NAND should continue to improve in the future as layer counts hit 176, 256, and beyond.
[*] SLC, MLC, TLC, and QLC explainer.
Also at Guru3D.
See also: Memblaze's PBlaze5 X26: Toshiba's XL-Flash-Based Ultra-Low Latency SSD
Related: Western Digital and Samsung at the Flash Memory Summit
Samsung Shares Plans for 96-Layer TLC NAND, QLC NAND, and 2nd-Generation "Z-NAND"
Western Digital's Low Latency Flash: A Competitor to Intel's Optane (3D XPoint)?
Western Digital Develops Low-Latency Flash to Compete with Intel Optane
Western Digital is working on its own low-latency flash memory that will offer a higher performance and endurance when compared to conventional 3D NAND, ultimately designed to compete against Optane storage.
At Storage Field Day this week, Western Digital spoke about its new Low Latency Flash NAND. The technology is meant to fit somewhere between 3D NAND and DRAM, similar to Intel's Optane storage and Samsung's Z-NAND. Similar to those technologies, according to Western Digital, its LLF memory will feature access time "in the microsecond range", using 1 bit-per-cell and 2 bit-per-cell architectures.
[...] Western Digital does not disclose all the details regarding its low-latency flash memory and it is impossible to say whether it has anything to do with Toshiba's XL-Flash low-latency 3D NAND introduced last year as well as other specialized types of flash.
[...] In the more long term, Western Digital is working on ReRAM-based SCM internally, and on memristor-based SCM with HP.
The estimate is that WD's LLF memory will be 1/10th the cost of DRAM, and 3x as expensive as 3D NAND.
This sounds like a rebrand of SLC and MLC NAND.
Related: SanDisk and HP Announce Potential Competitor to XPoint Memory
IBM Demonstrates Phase Change Memory with Multiple Bits Per Cell
Western Digital and Samsung at the Flash Memory Summit
Fujitsu to Mass Produce Nantero-Licensed NRAM in 2018
Rambus and Gigadrive Form Joint Venture to Commercialize Resistive RAM
Samsung Shares Plans for 96-Layer TLC NAND, QLC NAND, and 2nd-Generation "Z-NAND"
Crossbar Searching for Funding and Customers for its ReRAM Products to Compete with Intel's Optane
Samsung Announces Mass Production of Commercial Embedded Magnetic Random Access Memory (eMRAM)
While other manufacturers are making 512 Gb to 1 Tb 3D NAND flash dies, Toshiba is using through-silicon vias (TSVs) to stack their dies, effectively cramming 384 to 768 layers of 3D NAND into a single chip. Toshiba announced that it was developing this capability back in 2015, and now the first products to use it will be available in 2018:
Toshiba on Wednesday introduced its first BiCS 3D TLC NAND flash chips with 512 GB and 1 TB capacities. . The new ICs stack 8 or 16 3D NAND devices using through silicon vias (TSVs) and are currently among the highest capacity non-volatile memory stacks available in the industry. Commercial products powered by the 512 GB and 1 TB packages are expected to hit the market in 2018, with an initial market focus on high-end enterprise SSDs
Stacking NAND devices to build high capacity flash memory ICs has been used for years to maximize the capacities and performance of SSDs and other solid state storage devices. In many cases, NAND makers use wire-bonding technique to stack multiple memory devices, but it makes packages larger and requires a lot of power for reliable operation. However in more recent years, Toshiba has adopted TSV techniques previously used for ASIC and DRAM devices to stack its NAND ICs, which has enabled it to shrink size of its NAND packages and reduce their power consumption.
TSVs are essentially electrodes that penetrate the entire thickness of a silicon die and connect the dies above and below it in the stack. A bus formed by TSVs can operate at a high data transfer rate, consume less power, and take up less space than a bus made using physical wires. Since 3D NAND is based on vertically stacked memory layers and has numerous vertical interconnects, so far Toshiba has not used TSVs to interconnect such devices. To wed TSV and 3D NAND, Toshiba had to develop a special 512 Gb BiCS NAND die featuring appropriate electrical conductors.
The devices both measure 14 mm × 18 mm. The 8-stack chip has a height of 1.35 mm, and the 16-stack chip has a height of 1.85 mm.
Rambus, GigaDevice form ReRAM joint venture
Reliance Memory has been formed in Beijing, China to commercialize Resistive Random Access Memory (ReRAM) technology. The company is a joint venture between intellectual property developer Rambus Inc. (Sunnyvale, Calif.), fabless chip company GigaDevice Semiconductor (Beijing) Inc. and multiple venture capital companies. VC companies include THG Ventures, West Summit Capital, Walden International and Zhisland Capital.
The value of the investment was not disclosed but the company is expected to make ReRAM for use in embedded and IoT applications. GigaDevice is a fabless chip company that uses foundries to manufacture non-volatile memory and 32bit microcontrollers.
The Rambus ReRAM technology, previously known as CMOx has a heritage that goes back to Rambus's acquisition of Unity Semiconductor Corp. for $35 million in February 2012. Unity has been working on the technology for a decade, but failed to bring the technology to market. Unity had claimed to have developed a passive rewritable cross-point memory array based on conductive metal oxide. This would provide similarities to filament-based metal migration technologies such as those developed by Adesto Technologies Corp. and Crossbar Inc.
Resistive random-access memory. Yes, that Rambus.
Related: Crossbar 3D Resistive RAM Heads to Commercialization
Intel-Micron's 3D XPoint Memory Lacks Key Details
IBM Demonstrates Phase Change Memory with Multiple Bits Per Cell
HP/HPE's Memristor: Probably Dead
Western Digital and Samsung at the Flash Memory Summit
Fujitsu to Mass Produce Nantero-Licensed NRAM in 2018
A number of companies have made announcements related to 64-layer 3D NAND production and products at Computex 2017:
64-layer NAND, and subsequently products with the technology, will make the largest splash at Computex 2017 this week. Toshiba, Western Digital, and SanDisk have product announcements in queue, with others set to follow. Toshiba already released some information about the technology at Dell World, so the other shoe has to drop from manufacturing partner WD. This is the moment many of us have waited for.
In short, Toshiba/WD are supposed to take us out of the NAND recession by delivering third-generation 3D NAND called BiCS FLASH.
BiCS FLASH may gain praise for reducing the strain on NAND supply, but our readers will be left behind for several quarters. SanDisk has said for years that the future focus will be on 3-bit per cell NAND (or TLC). That philosophy carried over to infect Western Digital after the SanDisk acquisition. No one talks about BiCS MLC for use in the client space, even though 3D TLC is unproven technology for high-performance products (outside of Samsung).
(Score: 2) by jmorris on Saturday August 13 2016, @11:41PM
This is just one of a family of products trying to fit themselves between RAM and FLASH and try to carve out a niche while the cost, capacity and such of all three (RAM, FLASH and each SCM candidate) techs will rapidly vary. One or more will get smashed into the edges of those cost curves and die and there will be very little margin for error. The goal has to be replacing either RAM or FLASH before that happens and opening out the range they can operate in.
Replacing RAM is proving much harder than the optimistic early days of HP's dreams of building The Machine with TBs of RAM and no secondary storage. If your product's data sheet or marketing materials even mentions the word 'endurance' it isn't a RAM replacement candidate. If running Memtest86 overnight will destroy it, it isn't RAM.
On the other edge, FLASH already has one heck of a head start but as endurance is dropping like a stone as capacity increases it seems to be hitting some hard physical limits. The smart money would therefore be on taking out FLASH with a replacement tech. A machine with a non-uniform memory map, a few GB of RAM followed by a few TBs of kinda/sorta RAM would be an interesting model for a lot more than just enterprise use as a caching layer between memory and the SAN. Widespread availability should set off a whole new round of software development to use it.
(Score: 0) by Anonymous Coward on Saturday August 13 2016, @11:53PM
A machine with a non-uniform memory map, a few GB of RAM followed by a few TBs of kinda/sorta RAM would be an interesting model for a lot more than just enterprise use as a caching layer between memory and the SAN.
Doesn't putting your swap files/partitions, depending on the OS, onto the SSD achieve this?
(Score: 2) by jmorris on Sunday August 14 2016, @01:59AM
No. An SSD is a lot faster than a spinning disc but not in the same ballpark with something sitting in a DIMM socket. The problem is that while some of the current candidates can approach DRAM access times for read and under the right blocking conditions at least get in the ballpark for writes, the endurance limit mandates that it be treated very differently than real RAM.
The problem is error correction. All current flash is as unreliable as a hard drive, bit errors are routine and expected, but that requires an error correction pass on every read instead of a rare exception as with ECC DRAM. Forget access times measured in nanoseconds if you have to pull an entire memory block into a scratch space and run error correction across it. I'm afraid these new techs will prove unreliable enough when scaled to giga capacity that they will also need extensive error correction, again making them more a replacement for flash instead of ram.
(Score: 2) by takyon on Sunday August 14 2016, @12:11AM
3D/vertical scaling has done wonders for NAND though, delaying endurance issues for at least a decade.
The ITRS 2015 report [semiconductors.org] has some interesting predictions that may be conservative (page 33 of the report, 43 of the PDF). 512 layers by 2030. That's a number no manufacturer has been willing to throw out, but we know they might be able to get to numbers like 128 and 192 by string stacking 64 layer dies. The table lists production of 768 Gbit @64-96 layers in 2020, but as we can see in the summary Samsung is doing 512 Gb @ 64 layers already. From Samsung's press release [legitreviews.com], we find out that "Samsung plans to provide the world’s first 4th generation V-NAND flash memory products in the fourth quarter of this year". Samsung's first generation of V-NAND was "introduced" in August 2013. So we are seeing new generations at a rate of more than one a year.
The same WD slide mentioned in the summary has the $/GB gap between SCM and 3D BiCS NAND staying constant, while the gap between SCM and DRAM widens. That and other commentary leads me to believe that SCM/XPoint/Crossbar/etc. tier will make gains at the expense of DRAM, not NAND.
The ITRS page has DRAM density quadrupling between 2015 and 2030, while NAND density increases 16x.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by takyon on Sunday August 14 2016, @12:14AM
For some reason the space between "@" and "64" in "768 Gbit @ 64-96 layers" disappears in the comment preview and posting. It requires both of the links apparently.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by takyon on Sunday August 14 2016, @12:31AM
Actually, it requires just the second link:
A @B space should be before the B AAAAAAAAHHHHH [google.com]
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by jmorris on Sunday August 14 2016, @02:04AM
They are still losing ground. Old school SLC flash had 100,000+ write endurance. MLC Flash fell to 10,000 and this new TLC is rated for only 1,000 writes. Even if they can hold that 1,000 figure as they scale up the number of bits per cell they are already in territory where I for one wouldn't like buying anything with the stuff soldered down to the main system board. So they are likely left just scaling layers, leaving out more dense coding and die shrinks. Not good. Once your capacity growth is strictly limited to stacking physical bits into ever more complex structures you probably leave Moore's Law behind and a competitor has an opportunity.
(Score: 2) by takyon on Sunday August 14 2016, @02:27AM
No, I don't think so [eetimes.com]:
Because of the larger process node.
I'm not sure about 3rd or 4th gen 3D NAND, but it's sure higher than 1,000 writes. It might even still be at 20k.
Pretty soon, almost all NAND will be 3D NAND (you can use DRAM or SCM/XPoint/whatever as a cache instead of... 3D SLC?). Maybe in the future we will see a low endurance offshoot where the process node shrinks to ~15nm along with adding more layers. Plenty of customers could use NAND that isn't rated for multiple drive writes per day for cold storage purposes.
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(Score: 2) by Scruffy Beard 2 on Sunday August 14 2016, @06:38AM
Write endurance also tells you how long you can leave it on the shelf.
The old SLC NAND could store data for about 100 years... after the first write. It goes down from there as you wear down the gate insulation.
(Score: 2) by takyon on Sunday August 14 2016, @12:08PM
All Amazon Glacier has to do is fire it up every year or two, right?
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(Score: 2) by Scruffy Beard 2 on Sunday August 14 2016, @01:17PM
I have heard that with MLC flash, just reading it degrades the information.