A nanotube-based non-volatile RAM product could give Intel/Micron's 3D XPoint some competition:
Fujitsu announced that it has licensed Nantero's carbon nanotube-based NRAM (Non-volatile RAM) and will participate in a joint development effort to bring a 256Gb 55nm product to market in 2018. Carbon nanotubes are a promising technology projected to make an appearance in numerous applications, largely due to their incredible characteristics, which include unmatchable performance, durability and extreme temperature tolerance. Most view carbon nanotubes as a technology far off on the horizon, but Nantero has had working prototypes for several years.
[...] Other products also suffer limited endurance thresholds, whereas Nantero's NRAM has been tested up to 10^12 (1 trillion) cycles. The company stopped testing endurance at that point, so the upper bounds remain undefined. [...] The NRAM carbon nanotubes are 2nm in diameter. Much like NAND, fabs arrange the material into separate cells. NAND employs electrons to denote the binary value held in each cell (1 or 0), and the smallest lithographies hold roughly a dozen electrons per cell. NRAM employs several hundred carbon nanotubes per cell, and the tubes either attract or repel each other with the application of an electrical current, which signifies an "on" or "off" state. NRAM erases (resets) the cells with a phonon-driven technique that forces the nanotubes to vibrate and separate from each other. NRAM triggers the reset process by reversing the current, and it is reportedly more power efficient than competing memories (particularly at idle, where it requires no power at all).
NRAM could be much faster than 3D XPoint and suitable as universal memory for a concept like HP's "The Machine":
NRAM seems to be far faster than XPoint, and could be denser. An Intel Optane DIMM might have a latency of [7-9 µs] (7,000-9,000ns). Micron QuantX XPoint SSDs are expected to have latencies of [10 µs] for reading and [20 µs] for writing; that's 10,000 and 20,000ns respectively. A quick comparison has NRAM at c50ns or less and XPoint DIMMs at 7,000-10,000ns, 140-200 times slower. We might imagine that an XPoint/ReRAM-using server system has both DRAM and XPoint/ReRAM whereas an NRAM-using system might just use NRAM, once pricing facilitates this.
Another company licensing with Nantero is already looking to scale the NRAM down to 28nm.
Related Stories
Rambus, GigaDevice form ReRAM joint venture
Reliance Memory has been formed in Beijing, China to commercialize Resistive Random Access Memory (ReRAM) technology. The company is a joint venture between intellectual property developer Rambus Inc. (Sunnyvale, Calif.), fabless chip company GigaDevice Semiconductor (Beijing) Inc. and multiple venture capital companies. VC companies include THG Ventures, West Summit Capital, Walden International and Zhisland Capital.
The value of the investment was not disclosed but the company is expected to make ReRAM for use in embedded and IoT applications. GigaDevice is a fabless chip company that uses foundries to manufacture non-volatile memory and 32bit microcontrollers.
The Rambus ReRAM technology, previously known as CMOx has a heritage that goes back to Rambus's acquisition of Unity Semiconductor Corp. for $35 million in February 2012. Unity has been working on the technology for a decade, but failed to bring the technology to market. Unity had claimed to have developed a passive rewritable cross-point memory array based on conductive metal oxide. This would provide similarities to filament-based metal migration technologies such as those developed by Adesto Technologies Corp. and Crossbar Inc.
Resistive random-access memory. Yes, that Rambus.
Related: Crossbar 3D Resistive RAM Heads to Commercialization
Intel-Micron's 3D XPoint Memory Lacks Key Details
IBM Demonstrates Phase Change Memory with Multiple Bits Per Cell
HP/HPE's Memristor: Probably Dead
Western Digital and Samsung at the Flash Memory Summit
Fujitsu to Mass Produce Nantero-Licensed NRAM in 2018
Crossbar, which has talked up its version of a post-NAND memory/storage technology for years with little to show for it, now has to compete with the elephant in the room:
Crossbar, developer of Resistive RAM (ReRAM) chips, is setting up an AI consortium to help counter, er, resistance to the technology, speed up its adoption, and hopefully outrun Intel's Optane.
ReRAM is a type of non-volatile memory with DRAM-class access latency. So, flash-style solid-state storage with RAM-ish access. However, it is taking a long time to mature into a practical technology that can be deployed in devices to fill the gap between large-capacity, non-volatile, relatively slow NAND, and high-speed, relatively low capacity, volatile DRAM.
[...] Crossbar claims it can design "super dense 3D cross-point arrays, stackable with the capability to scale below 10nm, paving the way for terabytes on a single die." Beat that, Optane. Check out a white paper from the upstart here (registration needed.)
Crossbar continued to develop its ReRAM, inking a licensing agreement with Microsemi in May last year, involving the use of sub-10nm ReRAM tech in coming Microsemi products.
[...] Crossbar says it's working with Japanese authorities to review opportunities for the 2020 Olympics, including video-based event detection and response capability. We'll see if anything comes of that.
Previously: Crossbar 3D Resistive RAM Heads to Commercialization
Related: SanDisk and HP Announce Potential Competitor to XPoint Memory
Fujitsu to Mass Produce Nantero-Licensed NRAM in 2018
Two Resistive Random Access Memory (RRAM) Papers
Intel Announces the Optane SSD 900P: Cheaper 3D XPoint for Desktops
Intel Unveils 58 GB and 118 GB Optane SSDs
Rambus and Gigadrive Form Joint Venture to Commercialize Resistive RAM
Micron Buys Out Intel's Stake in 3D XPoint Joint Venture
Western Digital Develops Low-Latency Flash to Compete with Intel Optane
Western Digital is working on its own low-latency flash memory that will offer a higher performance and endurance when compared to conventional 3D NAND, ultimately designed to compete against Optane storage.
At Storage Field Day this week, Western Digital spoke about its new Low Latency Flash NAND. The technology is meant to fit somewhere between 3D NAND and DRAM, similar to Intel's Optane storage and Samsung's Z-NAND. Similar to those technologies, according to Western Digital, its LLF memory will feature access time "in the microsecond range", using 1 bit-per-cell and 2 bit-per-cell architectures.
[...] Western Digital does not disclose all the details regarding its low-latency flash memory and it is impossible to say whether it has anything to do with Toshiba's XL-Flash low-latency 3D NAND introduced last year as well as other specialized types of flash.
[...] In the more long term, Western Digital is working on ReRAM-based SCM internally, and on memristor-based SCM with HP.
The estimate is that WD's LLF memory will be 1/10th the cost of DRAM, and 3x as expensive as 3D NAND.
This sounds like a rebrand of SLC and MLC NAND.
Related: SanDisk and HP Announce Potential Competitor to XPoint Memory
IBM Demonstrates Phase Change Memory with Multiple Bits Per Cell
Western Digital and Samsung at the Flash Memory Summit
Fujitsu to Mass Produce Nantero-Licensed NRAM in 2018
Rambus and Gigadrive Form Joint Venture to Commercialize Resistive RAM
Samsung Shares Plans for 96-Layer TLC NAND, QLC NAND, and 2nd-Generation "Z-NAND"
Crossbar Searching for Funding and Customers for its ReRAM Products to Compete with Intel's Optane
Samsung Announces Mass Production of Commercial Embedded Magnetic Random Access Memory (eMRAM)
(Score: 0, Disagree) by Anonymous Coward on Thursday September 01 2016, @11:31AM
server system has both DRAM and XPoint/ReRAM whereas an NRAM-using system might just use NRAM, once pricing facilitates this.
10^12 (1 trillion) cycles / 2*10^9 cycles (2 GHz) = 500 seconds
Seems that for a long time DRAM is still going to be needed.
(Score: 0) by Anonymous Coward on Thursday September 01 2016, @01:58PM
It takes 10,000-20000 ns to write 1 cell. But your idea is sound.
But to give you an idea most current SSDs have a cell rewrite in about 1000 to 30000 depending on feature size and usage case.
(Score: 3, Informative) by TheRaven on Thursday September 01 2016, @03:32PM
One cycle is a rewrite cycle. If it takes 1µs to toggle a bit, then you'd need 16.5 weeks of constantly toggling the same bit to wear it out. Even stack memory (which would be totally insane to put in NVRAM) isn't written at the full interface bandwidth though.
At maximum performance, DDR4 (currently the state of the art DRAM interface standard) allows 19.2GB/s transfers. If you have 32GiB of RAM in your server per DDR4 channel (slightly on the low end, but not too far off), then if your writes all average out to a uniform distribution (best possible case), then it will take 1.79 seconds to toggle every bit once. That works out to 56,750 years to manage to write all of it. If you manage 0.01% of this, then your server is lasting pretty well. 0.01% of ideal wear levelling is pretty easily managed by providing write counters (even something very coarse to flag pages near their limits) to the OS and letting the virtual memory subsystem handle remapping. Even at superpage granularity, you should be able to do that (modern VM subsystems already move data around between physical pages to coalesce pages for superpage promotion). When a particular page gets close to having bits that have been flipped a trillion times, then you'll likely just mark it as CoW and prevent further writes.
sudo mod me up
(Score: 3, Insightful) by jmorris on Thursday September 01 2016, @07:11PM
All of which misses the point. If it has a write limit it isn't RAM. If you have to do wear leveling and error detection and correction is routine instead of a very rare exception you can't use it as ram. You won't feed a modern CPU's cache if you you have a complex controller between the chips and the CPU that has to do that sort of work. Basically we have three levels now. RAM has access times in nanoseconds, Flash/SSD is microseconds and spinning media in milliseconds.
(Score: 0) by Anonymous Coward on Friday September 02 2016, @02:21AM
The company stopped testing endurance at that point, so the upper bounds remain undefined
They dont know the upper limit.
(Score: 3, Informative) by TheRaven on Friday September 02 2016, @08:30AM
If it has a write limit it isn't RAM.
So DRAM isn't RAM? The capacitors degrade over time while holding charge. They just degrade sufficiently slowly that most of the time you'll throw the RAM away long before it dies. It sounds like NRAM is also in this category for a lot of usage models.
You won't feed a modern CPU's cache if you you have a complex controller between the chips and the CPU that has to do that sort of work
You already have a complex controller between the chips and the CPU, it's called an MMU. On everything except MIPS these days it has a TLB (actually, typically multiple levels of TLB) and a hardware page-table walker that will fill the TLB. The only thing required to be able to do wear levelling at page granularity would be a mechanism for the OS to query the RAM. You probably wouldn't do this with write counters, you'd do it by triggering ECC recoverable error reports when the value of a 1 or 0 is sufficiently close to the threshold that it probably isn't going to last much longer. All that the OS needs to do is then move the data to a different physical page and update the page table. That's something that some server operating systems do already for ECC memory (don't trust lines that keep reporting recoverable errors).
With a trillion writes before it starts to look unreliable, we're not talking about something that's common, we're talking about having to be a bit more careful with how you handle ECC failures because now the data in your RAM is likely to be important persistent data, not just temporary results that can be discarded on reboot.
sudo mod me up
(Score: 0) by Anonymous Coward on Thursday September 01 2016, @01:43PM
I don't exepct this coming to PC anytime soon. The target market for this, surely, is datacenters. After the market stabilizes, one comes victorious. Just then we could be hoping to get a desktop board with support for this.
(Score: 3, Informative) by hendrikboom on Thursday September 01 2016, @02:09PM
Please use the correct abbreviation for microsecond, or spell microsecond out in full, or make it clear what you mean by explaining that 10 ms is 10,000,000 ns, in case that's what you mean.
(Score: 0) by Anonymous Coward on Thursday September 01 2016, @03:53PM
In case your keyboard settings don't allow you to enter the µ directly, you can just copy it from this post. Or use the HTML entity μ of course.
(Score: 2) by butthurt on Friday September 02 2016, @12:06AM
Alternatively, "u" is sometimes used by those who can't, or can't be bothered to, make the mu character.
(Score: 2) by Gravis on Thursday September 01 2016, @05:07PM
You need to be telling this to editors of The Register because that's where that excerpt comes from.
(Score: 2) by RamiK on Thursday September 01 2016, @07:25PM
*10^-9 FOREVER!!!11!!!
compiling...
(Score: 3, Insightful) by Runaway1956 on Thursday September 01 2016, @03:38PM
So, the FBI is kicking my door down, and I reboot the computer. They don't care, because system state comes right back up, like laptop sleep? Time to start rethinking a few things about computer usage. Security takes on a whole different aspect.
(Score: 1, Flamebait) by Azuma Hazuki on Thursday September 01 2016, @05:48PM
You could just, you know, not browse the skinhead and bestiality sites in the first place...
I am "that girl" your mother warned you about...
(Score: 2) by DannyB on Thursday September 01 2016, @06:11PM
Legal adults have a right to read or view any legal material that they want. Anyone else opinion of it is irrelevant.
Unless the government has a warrant, they have no right to rummage through your physical or digital belongings.
The government has demonstrated a complete disregard for personal privacy in both stored files and communications. It has also demonstrated that it will gleefully look for any reason to arrest you that it can make up or contrive. Therefore, it seems reasonable that everyone take digital security seriously. If the powers that be don't like it, boo hoo! They brought it on themselves.
To transfer files: right-click on file, pick Copy. Unplug mouse, plug mouse into other computer. Right-click, paste.
(Score: 0) by Anonymous Coward on Thursday September 01 2016, @08:01PM
The government doesn't have any rights whatsoever; it has powers.
(Score: 2) by Runaway1956 on Thursday September 01 2016, @06:39PM
Not much of a skinhead - if I ever was a white supremacist, then I was disillusioned by some serious Darwin award candidates.
Beastiality? A couple girls have called me a beast.
But that's all beside the point. Let's say that I were in league with Guccifer and freinds. I'm hacking into the corrupt DNC, to find dirt on the candidate they forced on the public. The FBI is kicking down my door. With volatile memory, a reboot takes my system down, and system state is gone. With nonvolatile, does it come right back up, without asking for encryption keys, password, fingerprint, or whatever other security measures I have in place? System state. I most definitely want to disrupt/destroy the system state.
Looks like we'll need to come up with another method of destroying that system state. Hot keys to clear memory, then shut down?
Have you seen this story yet? http://www.foxnews.com/politics/2016/09/01/black-lives-matter-accuses-dems-placating-group-after-tactics-memo-leaked.html [foxnews.com]
(Score: 2) by Azuma Hazuki on Thursday September 01 2016, @07:21PM
I was joking, relax =P
But you're entirely right, nonvolatile RAM is a privacy disaster. The shutdown routine needs to do the equivalent of dd if=/dev/zero of=/dev/mem
I am "that girl" your mother warned you about...
(Score: 0) by Anonymous Coward on Friday September 02 2016, @05:58AM
(Score: 2) by Runaway1956 on Friday September 02 2016, @02:03PM
Well, yo mama is kinda horse faced . . .
(Score: 3, Informative) by butthurt on Friday September 02 2016, @12:00AM
The type of attack you're thinking about is already possible with the capacitive memory--so-called dynamic RAM (DRAM)--that we use now. It's called a "cold boot attack": at cryogenic temperatures, today's RAM retains its contents for hours.
https://en.wikipedia.org/wiki/Cold_boot_attack [wikipedia.org]
One approach to defending against it is the use of encrypted RAM. The trouble is, the encryption key needs to be stored somewhere.
http://tastytronic.net/~pedro/docs/ieee-hst-2010.pdf [tastytronic.net]
static RAM (SRAM) such as that built into microprocessors is, as far as I know, not subject to that attack: it stores information in transistors that are switched on or off. Once power is no longer applied, that information should vanish (unless I'm mistaken). DRAM is fast, expensive, and uses a lot of power. Keeping one's encryption keys in SRAM and encrypting the contents of RAM could be a viable way to defend against a cold boot attack (amusingly, such a defence would use the dynamic quality of static RAM to overcome the static quality of dynamic RAM). It might require SRAM that's separate from the microprocessor.
(Score: 3, Interesting) by TheRaven on Friday September 02 2016, @08:39AM
There's been some work on power-efficient GPU memory taking advantage of this by having longer refresh cycles for the lower bits. In most uses, users won't notice a 10% probability of bit flips in the lowest bit of a coordinate or colour. By gradually increasing the refresh cycle time, you have almost zero probability of error for the most significant bits, moving to quite low probability of error for the least significant bits. Particularly for memory that's being used as a render target (so if you do get bit flips, you'll recreate the data next frame anyway) this can give quite a big power saving without introducing artefacts that the user notices. Don't do this for scientific computing / GPGPU stuff though!
[1] Although a lot less bad than you'd think. A colleague of mine did some work a while ago showing that bit flips can allow you to escape from the JVM. As part of this, he held a hairdryer to the RAM chips to flip bits at random. It took quite an astonishing number of DRAM errors before most software noticed. It basically had to be a flip in a pointer, and often with alignment requirements it had to be either a very high bit or a low bit in a pointer to something that wasn't an array.
sudo mod me up
(Score: 2) by Geotti on Friday September 02 2016, @10:48AM
[...] this can give quite a big power saving without introducing artefacts that the user notices. Don't do this for scientific computing / GPGPU stuff though!
And don't do this with WOPR [wikipedia.org]!
(Score: 0) by Anonymous Coward on Thursday September 01 2016, @03:48PM
What is this "c" in "c50ns" supposed to stand for?
(Score: 0) by Anonymous Coward on Thursday September 01 2016, @05:53PM
My first guess would be "circa".