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posted by charon on Wednesday January 11 2017, @09:26PM   Printer-friendly
from the who's-a-cute-li'l-transistor? dept.

From Anandtech.com:

Qualcomm previously revealed the name of its new high-end SoC, but today at CES 2017 it discussed the Snapdragon 835 in greater detail. Replacing the Snapdragon 820/821 as the pinnacle processor in its lineup, the 835 is the first commercial SoC to use Samsung's 10nm "10LPE" FinFET manufacturing node. Qualcomm did not disclose die size, but it said the overall package size is 35% smaller than the Snapdragon 820 and contains more than 3 billion transistors. Samsung says its third-generation FinFET node "allows up to a 30% increase in area efficiency with 27% higher performance or up to 40% lower power consumption" relative to its first-generation 14nm 14LPE node at the same frequency, so Snapdragon 835's process advantage over the 820, which uses Samsung's second-generation 14LPP node, will be a bit less.

[...] Qualcomm finds itself in a much different position today compared to one year ago when it launched the Snapdragon 820. Back then, it was on the hot seat after its previous flagship products, the Snapdragon 808 and 810, failed to meet expectations. Qualcomm's implementation of ARM's Cortex-A57 CPU core and TSMC's last 20nm planar process were not a good combination, resulting in a generation of flagship phones that struggled to meet or exceed the performance of older models and exhibited higher than normal skin temperatures. The success of Snapdragon 820 would be crucial to regaining its partner's trust and restoring its image with consumers. The 820 was pivotal for another reason too: It introduced Qualcomm's first custom 64-bit CPU core, Kryo. Creating a custom CPU (or GPU/DSP/ISP) is one way for SoC vendors to differentiate their products and establish themselves as innovators. Snapdragon 810's use of stock ARM cores could be construed as a step backwards then after previous Snapdragon SoCs used Qualcomm's custom Krait CPUs. Apple's prior introduction of a custom 64-bit CPU, which caught everyone by surprise, only added fuel to the fire.


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Related Stories

Snapdragon 845 Announced 6 comments

Snapdragon 845 is a newly announced Qualcomm ARM system-on-a-chip (SoC) built on a 10nm "Low Power Plus" process. It is the first SoC to implement ARM's new DynamiQ clustering scheme:

The Snapdragon 845 is a large step in terms of SoC architectures as it's the first to employ ARM's DynamiQ CPU cluster organization. Quickly explained, DynamIQ enables the various different CPU cores within an SoC to be hosted within the same cluster and cache hierarchy, as opposed to having separate discrete clusters with no shared cache between them (with coherency instead happening over an interconnect such as ARM's CCI). This major transition is probably the largest to date that we've seen in modern mobile smartphone ARM consumer SoCs.

[...] The Kryo 385 gold/performance cluster runs at up to 2.8GHz, which is a 14% frequency increase over the 2.45GHz of the Snapdragon 835's CPU core. But we also have to remember that given that the new CPU cores are likely based on A75's we should be expecting IPC gains of up to 22-34% based on use-cases, bringing the overall expected performance improvement to 25-39%. Qualcomm promises a 25-30% increase so we're not far off from ARM's projections.

The silver/efficiency cluster is running at 1.8GHz, this is clocked slightly slower than the A53's on the Snapdragon 835 however the maximum clocks of the efficiency cluster is mainly determined by where the efficiency curve of the performance cluster intersects. Nevertheless the efficiency cores promise 15% boost in performance compared to its predecessor.

The Adreno 630 GPU should provide up to 30% better performance than the Snapdragon 835's Adreno 540 at the same level of power consumption. Snapdragon 845 devices can record (encode) 2160p60 10-bit H.265 video, compared to 2160p30 for Snapdragon 835.

Also at The Verge, CNET, TechCrunch, BGR, and 9to5Google.

Previously: Qualcomm's Snapdragon 835 Detailed: 3 Billion Transistors on a 10nm Process


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  • (Score: 1, Informative) by Anonymous Coward on Wednesday January 11 2017, @10:05PM

    by Anonymous Coward on Wednesday January 11 2017, @10:05PM (#452726)

    Qualcomm is a founding member [riscv.org] of the RISC-V Foundation; hopefully, they will start using this new, open, royalty-free, modular, forward-compatible ISA in place of ARM. The standard supports implementations from the embedded to the 128-bit general purpose, and from the single-core to the massively parallel.

    • (Score: 2) by Snotnose on Wednesday January 11 2017, @10:13PM

      by Snotnose (1623) on Wednesday January 11 2017, @10:13PM (#452729)

      I don't see that as happening. They're a founding member because they want to increase ARM marketshare. In their own top of the line chips they'll add their own secret sauce, which they''ll keep secret (heh).

    • (Score: 5, Informative) by TheRaven on Thursday January 12 2017, @11:25AM

      by TheRaven (270) on Thursday January 12 2017, @11:25AM (#452911) Journal

      Speaking as someone whose name you'll find in the acknowledgements of the RISC-V spec:

      RISC-V is a pretty good mid '90s ISA. ARMv8 is a good late '00s ISA. The lack of any kind of predication in RISC-V (not even a conditional move) simplifies the register forwarding but means that you either need complex microcode to spot short jumps with moves in the middle and turn them into conditional moves, or you need a lot more branch predictor state. Krste's argument for this is that it simplifies small implementations, but I had a student try adding a conditional move to RISC-V for a simple in-order pipeline and he found that you got less than 1% are increase from supporting it and needed 4 times the branch predictor state to achieve comparable performance without it (that wasn't a new result, by the way - it's the normal heuristic for conditional moves). Similarly, the relative lack of complex addressing modes in RISC-V vs ARM means that a lot of common operations require more instructions on RISC-V than ARM. The decision not to make the i-cache coherent with the d-cache means that, in a multicore system, any JIT compiler needs to call into the kernel, send IPIs, and do explicit invalidations, whereas the same effect is achieved almost for free via the cache coherency protocol on ARM (or x86). SPARC made this mistake too, but Java performance sucked so much on SPARC as a result that Sun fixed it in later revisions.

      Qualcomm's interest in RISC-V is primarily for a bunch of simple controllers on other things. A typical Qualcomm SoC contains a few dozen ARM cores, mostly M-class cores that are controlling other specialised cores. Replacing these with low-end RISC-V cores wouldn't make a difference to performance (even if they're slower - nothing these things do is stressing a low-end ARM core) and would reduce their per-SoC royalties by 10-20ยข. Micron is interested in RISC-V for a similar reason: every SSD controller board they ship has 7 ARM cores and in a market where the profit margin is a few dollars the royalty payments for these eat a lot of their profit.

      That's not to say that ARM should be complacent. The computing industry is full of the corpses companies that ignored a competitor that was only eating the low end of their business. Anyone remember SGI refusing to make a commodity GPU that would fit in a PC for fear of cannibalising their graphical workstation sales, only to have nVidia do it anyway?

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  • (Score: 2) by bob_super on Wednesday January 11 2017, @10:14PM

    by bob_super (1357) on Wednesday January 11 2017, @10:14PM (#452730)

    The title contains the same amount of information about the chip as TFS.
    Everything else is useless fluff about older process and older parts.

    Actually had to RTFA to learn something.
    I'm telling you, folks, it's a bad summary. bad! Terrible summary, folks.

    • (Score: 2) by JoeMerchant on Wednesday January 11 2017, @10:28PM

      by JoeMerchant (3937) on Wednesday January 11 2017, @10:28PM (#452740)

      Thank you for your useful distillation of TFA and supplement to the lacking summary.... oops, well, maybe not.

    • (Score: 2) by takyon on Wednesday January 11 2017, @10:35PM

      by takyon (881) <{takyon} {at} {soylentnews.org}> on Wednesday January 11 2017, @10:35PM (#452745) Journal

      Fake. The most important information is in the summary and not the headline:

      Samsung says its third-generation FinFET node "allows up to a 30% increase in area efficiency with 27% higher performance or up to 40% lower power consumption" relative to its first-generation 14nm 14LPE node at the same frequency

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      • (Score: 2) by ikanreed on Wednesday January 11 2017, @10:52PM

        by ikanreed (3164) on Wednesday January 11 2017, @10:52PM (#452754)

        So we're no longer in Moore's law land, but that's still quite the improvement.

        • (Score: 3, Interesting) by takyon on Thursday January 12 2017, @12:12AM

          by takyon (881) <{takyon} {at} {soylentnews.org}> on Thursday January 12 2017, @12:12AM (#452780) Journal

          Yeah, and the cluster arrangements of the 6, 8, 10 (+?) SoCs can take advantage of both the higher performance and lower power options. Although in the case of Snapdragon 835, it looks like it is using 8 equivalent cores.

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