from the beats-a-string-around-your-finger dept.
Samsung recently announced its fourth generation of 3D/vertical NAND, with 64 layers and a capacity of 512Gb (64GB) per die. Now SK Hynix is announcing its plans for 512 Gb V-NAND dies with 72 layers:
Later this year SK Hynix intends to start volume production of 72-layer 3D TLC NAND (3D-V4) memory and this is where things start to get interesting. Initially, SK Hynix intends to produce 256 Gb 3D TLC ICs and these are going to be available already in Q2 2017, according to the company's product catalog. Later on, sometimes in Q4, the company plans to introduce 512 Gb 3D TLC ICs (64 GB), which will help it to significantly increase capacities of SSDs and other devices featuring NAND flash.
What is important about SK Hynix's fourth-gen 3D NAND is that it will feature block size of 13.5 MB, which will increase the performance of such ICs compared to 3D-V3 and 3D-V2 that have a block size of 9 MB. At this point, we do not know whether SK Hynix intends to increase interface speed of its 512 Gb 3D-V4 ICs to compensate lower parallelism in lower-capacity SSDs, like Samsung did with its high-capacity 64-layer 3D V-NAND chips. What we do know is that SK Hynix's catalog already includes NAND multi-chip packages of 8192 Gb capacity (1 TB) that will enable high-capacity SSDs in smaller form-factors (e.g., [2 TB] single-sided M.2). Meanwhile, 64 GB NAND flash chips may force SK Hynix and its partners to abandon low-capacity SSDs (i.e., 120/128 GB) unless there is sufficient demand.
The article also talks about the company's plans for 18nm DRAM and fabrication facility expansion.
Toshiba and SanDisk have announced the development of a new 3D NAND product (called V-NAND by Samsung). It uses 48 layers of triple-level cell (TLC) NAND to store 256 Gb (32 GB) in a single die. It is expected to sample in September, and appear in solid-state drives and other products in the second half of 2016. However, the two companies will face plenty of competition. From Anandtech:
The new 3D NAND will face experienced competition from Samsung who are currently shipping 32-layer 3D NAND in capacities up to 128Gb for both MLC and TLC configurations. Samsung has also announced its third generation V-NAND which should be starting mass production in the latter half of this year. Meanwhile, Intel and Micron have stated that their 32-layer 3D NAND will be in mass production by the fourth quarter of this year in the form of a 256Gb MLC die and a 384Gb TLC die. SK Hynix is to begin mass production of a 36-layer 128Gb MLC die during the third quarter and is working toward a 48-layer TLC that will be available in 2016.
All of the major flash manufacturers have now publicized their plans for introducing 3D NAND. Planar NAND won't be disappearing overnight or even in a year, as it takes a lot of time and money to convert a fab to a new process. But from here on out, we can expect all the most interesting news about NAND flash memory to be about 3D.
The wide adoption of 3D/vertical NAND with increased feature sizes and endurance will apparently lead to the introduction of low-cost QLC (4 bits per cell) NAND. 3D NAND's increased flash cell size and overprovisioning will counteract the reduction in endurance caused by moving from 3 to 4 bits per cell:
We covered the TSV [Through Silicon Vias] notion here and now take a look at quadruple level cell (QLC) flash technology. Toshiba will present on this and TSVs in a keynote session at the August 6-9 Flash Memory Summit in Santa Clara. The session abstract notes: "New technologies such as QLC (Quadruple Level Cell) BiCS FLASH offer high density, low-cost solutions, while TSV (Through Silicon Via) NAND offers high performance with significant power reduction."
To recap, BiCS stands for Bit Cost Scalable and is Toshiba and flash foundry partner WDC's approach to 3D NAND, the layering of ordinary or planer (2D) NAND chips atop each other. We have 48-layer cells in production and 64-layer ones coming with 96-layer and even 128-layer chips in prospect. Progress beyond 64-layers has problems due to the difficulties in etching holes through the layers and so the TSV idea is to have two layers of layering: two 64-layer chips one on top of the other, with holes through them both, TSVs, for wiring to hold them together and carry out cell activity functions as well.
[...] Back in March, Jeff Ohshima, a Toshiba executive, presented on TSVs and QLC flash at the Non-Volatile Memory Workshop and suggested 88TB QLC 3D NAND SSDs with a 500 write cycle life could be put into production. The Flash Memory Summit keynote could add more colour to this.
Toshiba and SanDisk Announce 48-Layer 256 Gb 3D NAND
Toshiba Brings Through-Silicon Vias to NAND Flash
Western Digital, SanDisk, and the NAND Market
"String-Stacking" Being Developed to Enable 3D NAND With More Than 100 Layers (NAND devices with 64 layers and above will be difficult to create, so stacking 48-layer devices will be used to increase density)
Western Digital has announced its intention to include 3D Resistive RAM (ReRAM) as storage class memory (SCM) in future SSDs and other products:
Without making any significant announcements this week, Western Digital indicated that it would use some of the things it has learnt while developing its BiCS 3D NAND to produce its ReRAM chips. The company claims that its ReRAM will feature a multi-layer cross-point implementation, something it originally revealed a while ago.
Perhaps, the most important announcement regarding the 3D ReRAM by Western Digital is the claim about scale and capital efficiency of the new memory. Essentially, this could mean that the company plans to use its manufacturing capacities as well as its infrastructure (testing, packaging, etc.) in Yokkaichi, Japan, to make 3D ReRAM. Remember that SCM is at this point more expensive than NAND, hence, it makes sense to continue using the current fabs and equipment to build both types of non-volatile memory so ensure that the SCM part of the business remains profitable.
One of WD's slides projects SCM as 50% the cost per gigabyte of DRAM in 2017, declining to 5% by 2023.
Samsung introduced its fourth generation of vertical NAND, with 64 layers:
With a per-die capacity of 512Gb (64GB), Samsung can now put 1TB of TLC flash in a single package. This means most product lines will be seeing an increase in capacity at the high end of the range. Their BGA SSD products will be offering 1TB capacity even in the 11.5mm by 13mm form factor. The 16TB PM1633a SAS SSD will be eclipsed by the new 32TB PM1643. Likely to be further out, the PM1725 PCIe add-in card SSD will be succeeded by the PM1735 with a PCIe 4 x8 host interface.
Complementing the NAND update will be a new non-standard oversized M.2 form factor 32mm wide and 114mm long, compared to the typical enterprise M.2 size of 22mm by 110mm. A little extra room can go a long way, and Samsung will be using it to produce 8TB drives. These will be enterprise SSDs and Samsung showed a diagram of these enabling 256TB of flash in a 1U server. Samsung will also be producing 4TB drives in standard M.2 sizing.
In what is likely a bid to steal some thunder from 3D XPoint memory before it can ship, Samsung announced Z-NAND memory technology and a Z-SSD product based around Z-NAND and a new SSD controller. They said nothing about the operating principles of Z-NAND, but they did talk about their plans for the Z-SSD products.
64-layer 3D NAND is shipping, but the 256Gbit die will come and go rapidly. That's what makes this NAND cycle different. Many of the companies we've spoken to do not want to invest in products with such a limited shelf life. The 512Gbit die are right around the corner from the fabs. Some estimates put a major ramp up coming before mid year. The technology offers a 2x capacity increase while taking only a little more space on the wafer. The bits per wafer doesn't double, but it gets very close. The retail products coming in the second half of 2018 with have a heavy impact on SSD pricing. Some estimates from engineers we've spoken with put retail pricing on track for a 20% to 30% reduction over similar-capacity products shipping today.
Emerging technologies and form factors that reduce the material costs will also play a role. Toshiba Memory America showcased the new RC100 NVMe SSD that uses multi-chip packaging to cram the controller and flash in a single package.
Toshiba has described stacking 8-16 512 Gb dies with through silicon vias (TSVs) to create 512 GB and 1 TB packages. Samsung plans to stack 32 256 Gb dies to make 1 TB packages for an upcoming 128 TB SSD.
Previously: SK Hynix Plans 72-Layer 512 Gb NAND for Late 2017
SK Hynix Developing 96 and 128-Layer TLC 3D NAND
Intel First to Market With 64-Layer 3D NAND SSDs
Western Digital Announces 96-Layer 3D NAND, Including Both TLC and QLC
Toshiba's 3D QLC NAND Could Reach 1000 P/E Cycles
WD Announces 64-Layer 3D QLC NAND With 768 Gb Per Die, to be Shown at Flash Memory Summit
Samsung has announced a 30.72 TB SSD. It uses 64-layer 512 Gb TLC NAND dies, with 16 of each stacked to make a 1 TB package. It has 40 GB of DDR4 DRAM cache, also using layered packages:
The PM1643 drive also applies Through Silicon Via (TSV) technology to interconnect 8Gb DDR4 chips, creating 10 4GB TSV DRAM packages, totaling 40GB of DRAM. This marks the first time that TSV-applied DRAM has been used in an SSD.
Complementing the SSD's hardware ingenuity is enhanced software that supports metadata protection as well as data retention and recovery from sudden power failures, and an error correction code (ECC) algorithm to ensure high reliability and minimal storage maintenance. Furthermore, the SSD provides a robust endurance level of one full drive write per day (DWPD), which translates into writing 30.72TB of data every day over the five-year warranty period without failure. The PM1643 also offers a mean time between failures (MTBF) of two million hours.
Samsung started manufacturing initial quantities of the 30.72TB SSDs in January and plans to expand the lineup later this year – with 15.36TB, 7.68TB, 3.84TB, 1.92TB, 960GB and 800GB versions – to further drive the growth of all-flash-arrays and accelerate the transition from hard disk drives (HDDs) to SSDs in the enterprise market.
Related: SK Hynix Plans 72-Layer 512 Gb NAND for Late 2017
SK Hynix Developing 96 and 128-Layer TLC 3D NAND
Western Digital Announces 96-Layer 3D NAND, Including Both TLC and QLC
Toshiba Develops 512 GB and 1 TB Flash Chips Using TSV
Expect 20-30% Cheaper NAND in Late 2018
While other manufacturers are making 512 Gb to 1 Tb 3D NAND flash dies, Toshiba is using through-silicon vias (TSVs) to stack their dies, effectively cramming 384 to 768 layers of 3D NAND into a single chip. Toshiba announced that it was developing this capability back in 2015, and now the first products to use it will be available in 2018:
Toshiba on Wednesday introduced its first BiCS 3D TLC NAND flash chips with 512 GB and 1 TB capacities. . The new ICs stack 8 or 16 3D NAND devices using through silicon vias (TSVs) and are currently among the highest capacity non-volatile memory stacks available in the industry. Commercial products powered by the 512 GB and 1 TB packages are expected to hit the market in 2018, with an initial market focus on high-end enterprise SSDs
Stacking NAND devices to build high capacity flash memory ICs has been used for years to maximize the capacities and performance of SSDs and other solid state storage devices. In many cases, NAND makers use wire-bonding technique to stack multiple memory devices, but it makes packages larger and requires a lot of power for reliable operation. However in more recent years, Toshiba has adopted TSV techniques previously used for ASIC and DRAM devices to stack its NAND ICs, which has enabled it to shrink size of its NAND packages and reduce their power consumption.
TSVs are essentially electrodes that penetrate the entire thickness of a silicon die and connect the dies above and below it in the stack. A bus formed by TSVs can operate at a high data transfer rate, consume less power, and take up less space than a bus made using physical wires. Since 3D NAND is based on vertically stacked memory layers and has numerous vertical interconnects, so far Toshiba has not used TSVs to interconnect such devices. To wed TSV and 3D NAND, Toshiba had to develop a special 512 Gb BiCS NAND die featuring appropriate electrical conductors.
The devices both measure 14 mm × 18 mm. The 8-stack chip has a height of 1.35 mm, and the 16-stack chip has a height of 1.85 mm.
SSDs with 64 layers of 3D NAND are now available:
Today Intel is introducing their SSD 545s, the first product with their new 64-layer 3D NAND flash memory and, in a move that gives Intel a little bit of bragging rights, the first SSD on the market to use 64-layer 3D NAND from any manufacturer.
The Intel SSD 545s is a mainstream consumer SSD, which these days means it's using the SATA interface and TLC NAND flash. The 545s is the successor to last year's Intel SSD 540s, which was in many ways a filler product to cover up inconvenient gaps in Intel's SSD technology roadmap. When the 540s launched, Intel's first generation of 3D NAND was not quite ready, and Intel had no cost-competitive planar NAND of their own due to skipping the 16nm node at IMFT. This forced Intel to use 16nm TLC from SK Hynix in the 540s. Less unusual for Intel, the 540s also used a third-party SSD controller: Silicon Motion's SM2258. Silicon Motion's SSD controllers are seldom the fastest, but performance is usually decent and the cost is low. Intel's in-house SATA SSD controllers were enterprise-focused and not ready to compete in the new TLC-based consumer market.
[...] Intel will be using their smaller 256Gb 64L TLC die for all capacities of the 545s, rather than adopting the 512Gb 64L TLC part for the larger models. The 512Gb die is not yet in volume production and Intel plans to have the full range of 545s models on the market before the 512Gb parts are available in volume. Once the 512Gb parts are available we can expect to seem them used in other product families to enable even higher drive capacities, but it is reassuring to see Intel choosing the performance advantages of smaller more numerous dies for the mainstream consumer product range. Meanwhile, over the rest of this year, Intel plans to incorporate 64L 3D NAND into SSDs in every product segment. Most of those products are still under wraps, but the Pro 5450s and E 5100s are on the way as the OEM and embedded versions of the 545s.
SK Hynix is currently developing 96-layer and 128-layer 3D NAND with 3 bits per cell, but may be skipping quad-level cell 3D NAND for some time:
The 64-layer 3D NAND about to land from Micron and Toshiba certainly sounds impressive, but it pales in comparison to what Sk Hynix is working on for future release. The company is developing 96-layer and 128-layer 3D NAND flash. The new flash won't be available for a few years, but that makes it no less exciting. We have yet to see 72-layer 3D from Sk Hynix in our lab, but it will begin shipping soon in the PC401 using 256Gbit TLC die, according to the UNH-IOL list of tested products.
The information we found about the successor to 256Gbit 72-layer 3D TLC shows 96 layers with 512Gbit die capacity. The follow up to that is a massive 1Tbit die from 128-layer TLC from the other South Korean SSD manufacturer with full vertical integration.
Toshiba (or whichever company acquires Toshiba's memory division) may be more likely to introduce QLC 3D NAND.
A number of companies have made announcements related to 64-layer 3D NAND production and products at Computex 2017:
64-layer NAND, and subsequently products with the technology, will make the largest splash at Computex 2017 this week. Toshiba, Western Digital, and SanDisk have product announcements in queue, with others set to follow. Toshiba already released some information about the technology at Dell World, so the other shoe has to drop from manufacturing partner WD. This is the moment many of us have waited for.
In short, Toshiba/WD are supposed to take us out of the NAND recession by delivering third-generation 3D NAND called BiCS FLASH.
BiCS FLASH may gain praise for reducing the strain on NAND supply, but our readers will be left behind for several quarters. SanDisk has said for years that the future focus will be on 3-bit per cell NAND (or TLC). That philosophy carried over to infect Western Digital after the SanDisk acquisition. No one talks about BiCS MLC for use in the client space, even though 3D TLC is unproven technology for high-performance products (outside of Samsung).