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posted by CoolHand on Saturday March 18 2017, @02:15AM   Printer-friendly [Skip to comment(s)]
from the bigger-is-not-always-better dept.

Samsung has shipped 70,000 silicon wafers worth of "10nm Low Power Early" chips, and is planning a supposed 6 nanometer process. The company implies that it will make 8nm and 6nm chips in addition to 10nm and 7nm:

It's looking like Samsung will be the first company to manufacture 10nm chips, besting both Intel and TSMC. Samsung has also already set its eyes on the 8nm, 7nm, and 6nm process technologies. The 8nm and 6nm processes will likely be follow-up technologies to the 10nm and 7nm processes, respectively.

The company is expected to reach 7nm by 2019, a move that could be enabled by its partnership with IBM. The company may also use EUV lithography for its 7nm process, but it's not yet clear whether EUV lithography will be available for the first ever 7nm process iteration. Intel has hinted before that it may not adopt EUV lithography until the 5nm process generation. Samsung will reveal more details about its roadmap, including the 8nm and 6nm process generations, at the upcoming U.S Samsung Foundry Forum scheduled for May 24, 2017.

Samsung press release.


Original Submission

Related Stories

TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020 3 comments

Taiwan Semiconductor Manufacturing Company (TSMC) plans to make so-called "5nm" chips starting in early 2020:

TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC's 5 nm process starting from early 2020. When all three phases of the manufacturing facility are completed, its wafer starts capacity will exceed one million 300-mm wafers per year, comparable with other three GigaFabs operated by TSMC.

TSMC's Fab 18 will be located in Tainan (in the Southern Taiwan Science Park), and will be built in three phases. The construction of the first phase or segment of the building will be completed in about a year from now, after which TSMC will move in equipment sometime in early 2019. In about two years from now, the company expects to start volume production of chips using its 5 nm process technology at the Fab 18/phase 1. Construction of the second and the third phases will commence in Q3 2018 and Q3 2019. The two phases will start volume production in 2020 and 2021, respectively.

Extreme ultraviolet (EUV) lithography could be used to make "7nm" chips, but not "5nm" yet.

Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm


Original Submission

Samsung Plans to Make "5nm" Chips Starting in 2019-2020 5 comments

Samsung is preparing to manufacture 7LPP and 5LPE process ARM chips:

Samsung has said its chip foundry building Arm Cortex-A76-based processors will use 7nm process tech in the second half of the year, with 5nm product expected mid-2019 using the extreme ultra violet (EUV) lithography process.

The A76 64-bit chips will be able to pass 3GHz in clock speed. Back in May we wrote: "Arm reckoned a 3GHz 7nm A76 single core is up to 35 per cent faster than a 2.8GHz 10nm Cortex-A75, as found in Qualcomm's Snapdragon 845, when running mixed integer and floating-point math benchmarks albeit in a simulator."

[...] Samsung eventually envisages moving to a 3nm Gate-All-Round-Early (3AAE) on its process technology roadmap. Catch up, Intel, if you can.

Also at AnandTech.

Previously: Samsung Roadmap Includes "5nm", "4nm" and "3nm" Manufacturing Nodes

Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap (obsolete)
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process


Original Submission

Samsung's Second Generation 10nm-Class DRAM in Production 1 comment

Samsung's second generation ("1y-nm") 8 Gb DDR4 DRAM dies are being mass produced:

Samsung late on Wednesday said that it had initiated mass production of DDR4 memory chips using its second generation '10 nm-class' fabrication process. The new manufacturing technology shrinks die size of the new DRAM chips and improves their performance as well as energy efficiency. To do that, the process uses new circuit designs featuring air spacers (for the first time in DRAM industry). The new DRAM ICs (integrated circuits) can operate at 3600 Mbit/s per pin data rate (DDR4-3600) at standard DDR4 voltages and have been validated with major CPU manufacturers already.

[...] Samsung's new DDR4 chip produced using the company's 1y nm fabrication process has an 8-gigabit capacity and supports 3600 MT/s data transfer rate at 1.2 V. The new D-die DRAM runs 12.5% faster than its direct predecessor (known as Samsung C-die, rated for 3200 MT/s) and is claimed to be up to 15% more energy efficient as well. In addition, the latest 8Gb DDR4 ICs use a new in-cell data sensing system that offers a more accurate determination of the data stored in each cell and which helps to increase the level of integration (i.e., make cells smaller) and therefore shrink die size.

Samsung says that the new 8Gb DDR4 chips feature an "approximate 30% productivity gain" when compared to similar chips made using the 1x nm manufacturing tech.
UPDATE 12/21: Samsung clarified that productivity gain means increase in the number of chips per wafer. Since capacity of Samsung's C-die and D-die is the same, the increase in the number of dies equals the increase in the number of bits per wafer. Therefore, the key takeaway from the announcement is that the 1y nm technology and the new in-cell data sensing system enable Samsung to shrink die size and fit more DRAM dies on a single 300-mm wafer. Meanwhile, the overall 30% productivity gain results in lower per-die costs at the same yield and cycle time (this does not mean that the IC costs are 30% lower though) and increases DRAM bit output.

The in-cell data sensing system and air spacers will be used by Samsung in other upcoming types of DRAM, including DDR5, LPDDR5, High Bandwidth Memory 3.0, and GDDR6.

Also at Tom's Hardware.

Previously: Samsung Announces "10nm-Class" 8 Gb DRAM Chips

Related: Samsung Announces 12Gb LPDDR4 DRAM, Could Enable Smartphones With 6 GB of RAM
Samsung Announces 8 GB DRAM Package for Mobile Devices
Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Samsung Increases Production of 8 GB High Bandwidth Memory 2.0 Stacks
IC Insights Predicts Additional 40% Increase in DRAM Prices


Original Submission

Samsung Set to Outpace Intel in Semiconductor Revenues 8 comments

Based on current projections for sales and NAND/DRAM pricing, Samsung's semiconductor revenues are likely to grow larger than Intel's during the second quarter of 2017. Intel has held the #1 spot in the industry since 1993:

Samsung's positioning is strengthening not just because of increased demand for RAM and flash memory, but because an ongoing NAND shortage is keeping prices high. Analysts blame a rocky transition from 2D to 3D NAND, increased demand from Chinese smartphone manufacturers, and the increasing popularity of SSDs as factors in the shortage.

On top of the RAM business, Samsung also says it's seeing solid demand for 14nm SoCs, image sensors, and other smartphone chips. The company expects its new 10nm process to keep the business growing. Samsung manufactures its own Exynos SoCs as well as some of Qualcomm's Snapdragon chips and some of the A-series chips Apple uses across its iPhone, iPad, iPod, and Apple TV lineups.

IC Insights report.

Related:
Samsung's Exynos 8895 to be the First 10nm Chip on the Market
Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's


Original Submission

Samsung Roadmap Includes "5nm", "4nm" and "3nm" Manufacturing Nodes 10 comments

Samsung has replaced planned "6nm" and "5nm" nodes with a new "5nm" node on its roadmap, and plans to continue scaling down to "3nm", which will use gate-all-around transistors instead of Fin Field-effect transistors. Extreme ultraviolet lithography (EUV) will be required for everything below "7nm" (TSMC and GlobalFoundries will start producing "7nm" chips without EUV initially):

Last year Samsung said that its 7LPP manufacturing technology will be followed up by 5LPP and 6LPP in 2019 (risk production). The new roadmap does not mention either processes, but introduces the 5LPE (5 nm low power early) that promises to "allow greater area scaling and ultra-low power benefits" when compared to 7LPP. It is unclear when Samsung plans to start using 5LPE for commercial products, but since it is set to replace 7LPP, expect the tech to be ready for risk production in 2019.

[...] Samsung will have two 4 nm process technologies instead of one — 4LPE and 4LPP. Both will be based on proven FinFETs and usage of this transistor structure is expected to allow timely ramp-up to the stable yield level. Meanwhile, the manufacturer claims that their 4 nm nodes will enable higher performance and geometry scaling when compared to the 5LPE, but is not elaborating beyond that (in fact, even the key differences between the three technologies are unclear). Furthermore, Samsung claims that 4LPE/4LPP will enable easy migration from 5LPE, but is not providing any details.

[...] The most advanced process technologies that Samsung announced this week are the 3GAAE/GAAP (3nm gate-all-around early/plus). Both will rely on Samsung's own GAAFET implementation that the company calls MBCFET (multi-bridge-channel FETs), but again, Samsung is not elaborating on any details. The only thing that it does say is that the MBCFET has been in development since 2002, so it will have taken the tech at least twenty years to get from an early concept to production.

MBCFETs are intended to enable Samsung to continue increasing transistor density while reducing power consumption and increasing the performance of its SoCs. Since the 3GAAE/GAAP technologies are three or four generations away, it is hard to make predictions about their actual benefits. What is safe to say is that the 3GAAE will be Samsung's fifth-generation EUV process technology and therefore will extensively use appropriate tools. Therefore, the success of the[sic] EUV in general will have a clear impact on Samsung's technologies several years down the road.

Previously: Samsung Plans a "4nm" Process

Related: IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process


Original Submission

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  • (Score: 1, Insightful) by Anonymous Coward on Saturday March 18 2017, @02:57PM (1 child)

    by Anonymous Coward on Saturday March 18 2017, @02:57PM (#480854)

    Rename 14nm to 10nm. Gain free publicity to distract from bribery and combustion scandals.

    • (Score: 3, Informative) by richtopia on Saturday March 18 2017, @07:29PM

      by richtopia (3160) Subscriber Badge on Saturday March 18 2017, @07:29PM (#480898) Homepage Journal

      Unfortunately there isn't really an industry standard as to what node size is, particularly as we move to more and more 3d structures.

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