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posted by CoolHand on Thursday March 30 2017, @07:07PM   Printer-friendly
from the we-want-moore dept.

Intel is talking about improvements it has made to transistor scaling for the 10nm process node, and claims that its version of 10nm will increase transistor density by 2.7x rather than doubling it.

On the face of it, three years between process shrinks, rather than the traditional two years, would appear to end Moore's Law. But Intel claims that's not so. The company says that the 14nm and 10nm process shrinks in particular more than doubled the transistor density. At 10nm, for example, the company names a couple of techniques that are enabling this "hyperscaling." Each logic cell (an arrangement of transistors to form a specific logic gate, such as a NAND gate or a flip flop) is surrounded by dummy gates: spacers to isolate one cell from its neighbor. Traditionally, two dummy gates have been used at the boundary of each cell; at 10nm, Intel is reducing this to a single dummy gate, thereby reducing the space occupied by each cell and allowing them to be packed more tightly.

Each gate has a number of contacts used to join them to the metal layers of the chip. Traditionally, the contact was offset from the gate. At 10nm, Intel is stacking the contacts on top of the gates, which it calls "contact over active gate." Again, this reduces the space each gate takes, increasing the transistor density.

Intel proposes a new metric for measuring transistor density:

Intel wants to describe processes in terms of millions of logic transistors per square millimeter, calculated using a 3:2 mix of NAND cells and scan flip flop cells. Using this metric, the company's 22nm process managed 15.3 megatransistors per millimeter squared (MTr/mm2). The current 14nm process is 37.5MTr/mm2, and at 10nm, the company will hit 100.8MTr/mm2. Competing 14nm/16nm processes only offer around 28MTr/mm2, and Intel estimates that competing 10nm processes will come in at around 50MTr/mm2.

See also: the International Roadmap for Devices and Systems.

A number of stories here have covered the advancement to 10nm chips: Samsung: Exynos, TSMC: MediaTech Helio X30 for example. A reoccuring comment in the discussions is if 10nm from Samsung is equivalent to 10nm for TSMC or Intel.

Intel's Mark Bohr discussed the difficulty of comparing process nodes during Manufacturing Day, specifically proposing to move the industry to transistor density as a comparative metric. Surprisingly enough, Intel claims their 10nm process is roughly twice as dense of the competition. Intel is not the only ones frustrated by comparing process nodes, as this recent article tries to compare current "14nm" nodes between the major vendors.

To further confuse the discussion is new 22nm processes: Global Foundries 22nm FD-SOI and Intel's just announced 22FFL process, both targeting energy efficient devices. GF's is in high volume manufacturing already while Intel's is just announced, but further cement's Intel's delve into foundry work.

These topics are largely covered by EETimes' summary of Intel's recent announcements

Original Submission #1   Original Submission #2

Related Stories

Samsung's Exynos 8895 to be the First 10nm Chip on the Market 7 comments

Samsung will be the first company to sell a 10nm chip:

Samsung announced its next-generation mobile application processor, the Exynos 9 Series 8895, and said it's the first 10nm processor built so far. This means Samsung beat Intel and TSMC to the next-gen process node, but Qualcomm's Snapdragon 835 could soon follow on the same 10nm process.

The 10nm FinFET process brings an improved 3D transistor structure that allows for up to 27% higher performance or up to 40% power consumption when compared to Samsung's previous 14nm FinFET process.

Samsung said the Exynos 8895 is also the first chip to embed a gigabit LTE modem that supports five carrier aggregation (5CA). This allows wireless operators to combine multiple fragments of a spectrum to deliver higher data throughput. The modem can achieve up to 1Gbps (Cat. 16) downlink with 5CA, and 150 Mbps uplink with 2CA.

There's plenty of room at the bottom???

Original Submission

MediaTek Helio X30: 10 Cores on a 10nm Process 8 comments

MediaTek has released more details of an upcoming 10-core SoC:

MediaTek first unveiled the Helio X30—its next-generation high-end SoC—last fall, but today at Mobile World Congress the Taiwanese company announced its commercial availability. The Helio X30 is entering mass production and should make its debut inside a mobile device sometime in Q2 2017.

The Helio X30, like the Helio X20 family before it, incorporates 10 CPU cores arranged in a Max.Mid.Min tri-cluster configuration. Two of ARM's latest A73 CPU cores replace the two A72s in the Max cluster, which should improve performance and reduce power consumption. The Mid cluster still uses 4 A53 cores, but they receive a 10% frequency boost relative to the top-of-the-line Helio X27. In the X30's Min cluster we find the first implementation of ARM's most-efficient A-series core. The A35 consumes 32% less power than the A53 it replaces (same process/frequency), while delivering 80%-100% of the performance, according to ARM. With a higher peak frequency of 1.9GHz, the X30's A35 cores should deliver about the same or better performance than the X20's A53 cores and still consume less power.

Also at Tom's Hardware, entitled "The 10nm Helio X30 May Be MediaTek's First Truly Competitive High-End Chip".

While some smartphone SoCs like the X30 are a bit of an exception due to cluster configurations, there are going to be many CPUs with 8+ cores sold in 2017. Some examples that come to mind: AMD's Ryzen 7 desktop CPUs, the AMD APUs in the Xbox One, PS4, and PS4 Pro (with 7 cores usable in these consoles), and other smartphone SoCs like the Exynos 7 Octa 7880, which uses equivalent cores rather than clusters. Will games and popular applications be able to exploit this newfound glut of cores?

Related: Samsung's Exynos 8895 to be the First 10nm Chip on the Market

Original Submission

Samsung Set to Outpace Intel in Semiconductor Revenues 8 comments

Based on current projections for sales and NAND/DRAM pricing, Samsung's semiconductor revenues are likely to grow larger than Intel's during the second quarter of 2017. Intel has held the #1 spot in the industry since 1993:

Samsung's positioning is strengthening not just because of increased demand for RAM and flash memory, but because an ongoing NAND shortage is keeping prices high. Analysts blame a rocky transition from 2D to 3D NAND, increased demand from Chinese smartphone manufacturers, and the increasing popularity of SSDs as factors in the shortage.

On top of the RAM business, Samsung also says it's seeing solid demand for 14nm SoCs, image sensors, and other smartphone chips. The company expects its new 10nm process to keep the business growing. Samsung manufactures its own Exynos SoCs as well as some of Qualcomm's Snapdragon chips and some of the A-series chips Apple uses across its iPhone, iPad, iPod, and Apple TV lineups.

IC Insights report.

Samsung's Exynos 8895 to be the First 10nm Chip on the Market
Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's

Original Submission

CPU Rumor Mill: Intel Core i9, AMD Ryzen 9, and AMD "Starship" 9 comments

AMD is rumored to be releasing a line of Ryzen 9 "Threadripper" enthusiast CPUs that include 10, 12, 14, or 16 cores. This is in contrast to the Ryzen lines of AMD CPUs that topped out at the 8-core Ryzen 7 1800X with a base clock of 3.6 GHz.

Meanwhile, Intel is supposedly planning to release 6, 8, 10, and 12 core Skylake-X processors under an "Intel Core i9" designation. Two Kaby Lake-X, a quad-core and another quad-core with hyper-threading disabled, are also mentioned.

Finally, AMD's 32-core "Naples" server chips could be succeeded in late 2018 or 2019 by a 48-core 7nm part nicknamed "Starship". GlobalFoundries plans to skip the 10nm node, and where GF goes, AMD follows. Of course, according to Intel, what really matters are transistors per square millimeter.

All of the processors mentioned could be officially announced at Computex 2017, running from May 30 to June 3. Expect the high end desktop (HEDT) CPUs to be in excess of $500 and as high as $1,500. Intel may also announce Coffee Lake CPUs later this year including a "mainstream" priced 6-core chip.

Original Submission

Samsung Plans a "4nm" Process 12 comments

Samsung has added a so-called "4nm" process to its roadmap:

At the annual Samsung Foundry Forum, Samsung announced its foundry's roadmap for the next few years, which includes an 18nm FD-SOI [(Fully Depleted – Silicon on Insulator)] generation targeting low-cost IoT chips as well as 8nm, 7nm, 6nm, 5nm, and even 4nm process generations.

[...] 7LPP (7nm Low Power Plus): 7LPP will be the first semiconductor process technology to use an EUV lithography solution. 250W of maximum EUV source power, which is the most important milestone for EUV insertion into high volume production, was developed by the collaborative efforts of Samsung and ASML. EUV lithography deployment will break the barriers of Moore's law scaling, paving the way for single nanometer semiconductor technology generations.

[...] The 4LPP process generation will be Samsung's first to use a "Gate All Around FET" (GAAFET) transistor structure, with Samsung's own implementation dubbed "Multi Bridge Channel FET" (MBCFET). The technology uses a "Nanosheet" device to overcome the physical limitations of the FinFET architecture.


But how many transistors per square millimeter is it?

Original Submission

TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020 3 comments

Taiwan Semiconductor Manufacturing Company (TSMC) plans to make so-called "5nm" chips starting in early 2020:

TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC's 5 nm process starting from early 2020. When all three phases of the manufacturing facility are completed, its wafer starts capacity will exceed one million 300-mm wafers per year, comparable with other three GigaFabs operated by TSMC.

TSMC's Fab 18 will be located in Tainan (in the Southern Taiwan Science Park), and will be built in three phases. The construction of the first phase or segment of the building will be completed in about a year from now, after which TSMC will move in equipment sometime in early 2019. In about two years from now, the company expects to start volume production of chips using its 5 nm process technology at the Fab 18/phase 1. Construction of the second and the third phases will commence in Q3 2018 and Q3 2019. The two phases will start volume production in 2020 and 2021, respectively.

Extreme ultraviolet (EUV) lithography could be used to make "7nm" chips, but not "5nm" yet.

Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm

Original Submission

Samsung Plans to Make "5nm" Chips Starting in 2019-2020 5 comments

Samsung is preparing to manufacture 7LPP and 5LPE process ARM chips:

Samsung has said its chip foundry building Arm Cortex-A76-based processors will use 7nm process tech in the second half of the year, with 5nm product expected mid-2019 using the extreme ultra violet (EUV) lithography process.

The A76 64-bit chips will be able to pass 3GHz in clock speed. Back in May we wrote: "Arm reckoned a 3GHz 7nm A76 single core is up to 35 per cent faster than a 2.8GHz 10nm Cortex-A75, as found in Qualcomm's Snapdragon 845, when running mixed integer and floating-point math benchmarks albeit in a simulator."

[...] Samsung eventually envisages moving to a 3nm Gate-All-Round-Early (3AAE) on its process technology roadmap. Catch up, Intel, if you can.

Also at AnandTech.

Previously: Samsung Roadmap Includes "5nm", "4nm" and "3nm" Manufacturing Nodes

Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap (obsolete)
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process

Original Submission

Intel Denies that It Will Cancel or Skip its "10nm" Process 11 comments

Report: Intel is cancelling its 10nm process. Intel: No, we're not

Earlier today, it was reported that Intel is cancelling its troublesome 10nm manufacturing process. In an unusual response, the company has tweeted an official denial of the claims.

[...] The company's most recent estimate is that 10nm will go into volume production in the second half of 2019. The report from SemiAccurate cites internal sources saying that this isn't going to happen: while there may be a few 10nm chips, for the most part Intel is going to skip to its 7nm process.

Typically, Intel doesn't respond to rumors, but this one appears to be an exception. The company is tweeting that it's making "good progress" on 10nm and that yields are improving consistent with the guidance the company provided on its last earnings report. Intel's next earnings report is on Thursday, and we're likely to hear more about 10nm's progress then.

Also at Tom's Hardware and The Verge.

Related: Intel's "Tick-Tock" Strategy Stalls, 10nm Chips Delayed (it has been over 3 years since this article was posted)
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Intel's First 8th Generation Processors Are Just Updated 7th Generation Chips
Intel Releases Open Letter in Attempt to Address Shortage of "14nm" Processors and "10nm" Delays

Original Submission

Intel's Jim Keller Promises That "Moore's Law" is Not Dead, Outlines 50x Improvement Plan 17 comments

Intel's Senior Vice President Jim Keller (who previously helped to design AMD's K8 and Zen microarchitectures) gave a talk at the Silicon 100 Summit that promised continued pursuit of transistor scaling gains, including a roughly 50x increase in gate density:

Intel's New Chip Wizard Has a Plan to Bring Back the Magic (archive)

In 2016, a biennial report that had long served as an industry-wide pledge to sustain Moore's law gave up and switched to other ways of defining progress. Analysts and media—even some semiconductor CEOs—have written Moore's law's obituary in countless ways. Keller doesn't agree. "The working title for this talk was 'Moore's law is not dead but if you think so you're stupid,'" he said Sunday. He asserted that Intel can keep it going and supply tech companies ever more computing power. His argument rests in part on redefining Moore's law.

[...] Keller also said that Intel would need to try other tactics, such as building vertically, layering transistors or chips on top of each other. He claimed this approach will keep power consumption down by shortening the distance between different parts of a chip. Keller said that using nanowires and stacking his team had mapped a path to packing transistors 50 times more densely than possible with Intel's 10 nanometer generation of technology. "That's basically already working," he said.

The ~50x gate density claim combines ~3x density from additional pitch scaling (from "10nm"), ~2x from nanowires, another ~2x from stacked nanowires, ~2x from wafer-to-wafer stacking, and ~2x from die-to-wafer stacking.

Related: Intel's "Tick-Tock" Strategy Stalls, 10nm Chips Delayed
Intel's "Tick-Tock" is Now More Like "Process-Architecture-Optimization"
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Another Step Toward the End of Moore's Law

Original Submission

Intel CEO Blames "10nm" Delays on Aggressive Density Target, Promises "7nm" for 2021 10 comments

Intel says it was too aggressive pursuing 10nm, will have 7nm chips in 2021

[Intel's CEO Bob] Swan made a public appearance at Fortune's Brainstorm Tech conference in Aspen, Colorado, on Tuesday and explained to the audience in attendance that Intel essentially set the bar too high for itself in pursuing 10nm. More specifically, he pointed to Intel's overly "aggressive goal" of going after a 2.7x transistor density improvement over 14nm.

[...] Needless to say, the 10nm delays have caused Intel to fall well behind that transistor density doubling. Many have proclaimed Moore's Law as dead, but as far as Swan is concerned, Moore's Law is not dead. It apparently just needed to undergo an unexpected surgery.

"The challenges of being late on this latest [10nm] node of Moore's Law was somewhat a function of what we've been able to do in the past, which in essence was define the odds on scaling the infrastructure," Swan explains. Bumping up to a 2.7x scaling factor proved to be "very complicated," more so than Intel anticipated. He also says that Intel erred when it "prioritized performance at a time when predictability was really important."

"The short story is we learned from it, we'll get our 10nm node out this year. Our 7nm node will be out in two years and it will be a 2.0X scaling so back to the historical Moore's Law curve," Swan added.

Also at Fortune and Tom's Hardware.


Original Submission

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  • (Score: 3, Interesting) by kaszz on Thursday March 30 2017, @07:37PM

    by kaszz (4211) on Thursday March 30 2017, @07:37PM (#486690) Journal

    The price point will have a huge impact whether this sells or not in volumes large enough to motivate the R&D+fab investment. The transistors per area unit makes sense. But there may be caveats in interference, capacitance, heat dissipation and a lot of other issues when packing it tighter. I suppose the feature will measure the performance in logic switches per volume.

    Will be interesting to finding out the GHz of this new CPU. Supposedly there are 100 GHz transistors in the lab but designing a chip with them would just overheat. If this new technology just will enable more cores per chip then it may be cheaper to have more chips instead at the price of inter-core latency.

  • (Score: 2) by RamiK on Thursday March 30 2017, @07:45PM (5 children)

    by RamiK (1813) on Thursday March 30 2017, @07:45PM (#486693)

    I'm guessing out of every wafer, about 5% reaches 100MTr/mm^2. The rest have their defected transistors etched by the block until averaging at slightly over 50MTr/mm^2 like everyone else.

    • (Score: 2) by kaszz on Thursday March 30 2017, @07:49PM (4 children)

      by kaszz (4211) on Thursday March 30 2017, @07:49PM (#486697) Journal

      5% sounds like piss poor yield?

      (and bad business)

      • (Score: 2) by RamiK on Thursday March 30 2017, @09:11PM (3 children)

        by RamiK (1813) on Thursday March 30 2017, @09:11PM (#486750)

        If you get 100 chips off the wafer, 5 would be 100MTr/mm^2 and sold as top end Xeons. Another 5 would have a few circuits fused off ending up with 90MTr/mm^2 and sold as high mid-end... All the way down to i3 with, oh, say, 30-40MTr/mm^2 ? You can tell by how well GlobalFoundries compare against Intel with AMD's Ryzen at 14nm.

        Another way of looking at it is that the desktop users buying i7s are being over-charged by a wide margin as they're subsidizing the Xeons where Intel is forced to reduce the prices or face competition from IBM's POWER. Well, that bit of speculation will need to wait for Ryzen 5 and 3 and how well they compare.

        • (Score: 2) by kaszz on Thursday March 30 2017, @11:37PM (1 child)

          by kaszz (4211) on Thursday March 30 2017, @11:37PM (#486821) Journal

          Yeah that makes sense.

          And also infuriates the manufacturer when people finds out how to re-enable some functions ;-)

          • (Score: 2) by TheRaven on Friday March 31 2017, @09:59AM

            by TheRaven (270) on Friday March 31 2017, @09:59AM (#487008) Journal

            And also infuriates the manufacturer when people finds out how to re-enable some functions ;-)

            For two reasons. The 'evil' one is when they've disabled perfectly working features because the yields were higher than expected and there's more of a market for the low-end features (this was really common about 15-20 years ago). The more common reason is that these features are actually broken. They may work fine most of the time, but when the chip gets a bit warmer (but still well within its thermal design specification), they'll get unacceptable error rates. People who enable the features get crashy systems and blame the manufacturer.

            sudo mod me up
        • (Score: 0) by Anonymous Coward on Friday March 31 2017, @02:22PM

          by Anonymous Coward on Friday March 31 2017, @02:22PM (#487084)

          Can I put a Xenon in my desktop then? Or will the increased performance melt my consumer-grade motherboard?

  • (Score: 3, Informative) by takyon on Thursday March 30 2017, @07:49PM (3 children)

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Thursday March 30 2017, @07:49PM (#486698) Journal

    MIT Researchers Reveal More Efficient Way To Build Chips Below The 10nm Process []

    MIT researchers developed a new technique that allows chip structures to “self-assemble” at microscopic levels. The technique is said to be more cost-effective than extreme ultraviolet (EUV) lithography, another technique used in chip fabrication that’s expected to be used in 7nm and 5nm chips around 2020 or later.

    [...] A team of MIT researchers have developed a new technique called Direct Self-Assembly (DSA). This technique may help chip makers, especially those skeptical about EUV’s practicality in the short-term, to create 7nm or smaller chips.

    [...] According to the MIT team, the new process can be implemented using existing machinery with only small changes. This could make the technology more appealing to chip manufacturers, compared to using new lithography techniques to print much finer patterns.

    [...] One roadblock that the DSA technique could face is the fact that the lines formed by the chemical reactions may form structures that are too regular. The DSA technique may not work very well for chips with more irregular patterns, such as CPUs, but may work well enough for chips with much more regular patterns, such as memory chips.

    [SIG] 10/28/2017: Soylent Upgrade v14 []
    • (Score: 2) by Azuma Hazuki on Thursday March 30 2017, @07:52PM (2 children)

      by Azuma Hazuki (5086) on Thursday March 30 2017, @07:52PM (#486699) Journal

      Oh, thank God. EUV isn't anywhere near ready and this may be just what the doctor ordered to give standard etching another generation or two...

      I am "that girl" your mother warned you about...
      • (Score: 2) by kaszz on Thursday March 30 2017, @08:07PM (1 child)

        by kaszz (4211) on Thursday March 30 2017, @08:07PM (#486714) Journal

        Why is EUV so bad?

        • (Score: 3, Informative) by takyon on Thursday March 30 2017, @08:32PM

          by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Thursday March 30 2017, @08:32PM (#486733) Journal

          It's hard and expensive as heck, and 450mm wafers were supposed to make the transition to EUV easier, but haven't materialized.

          Intel's "Tick-Tock" Strategy Stalls, 10nm Chips Delayed []

          Intel will not be relying on the long-delayed extreme ultraviolet (EUV) lithography to make 10nm chips.

          Extreme ultraviolet lithography []

          What's the impact of 450-mm and EUV delays? [] (2010)

          This is what the death of Moore’s law looks like: EUV rollout slowed, 450mm wafers halted, and an uncertain path beyond 14nm [] (2014)

          One of the single greatest problems is source power. To put this simply — no one, including ASML, has yet demonstrated an EUV tool capable of reaching anything like the necessary power concentrations or of sustaining production volumes. Instead, we’re stuck at the red dot shown above. The enormous costs of shifting to EUV and 450mm wafers were meant to be partly offset by making the jump at the same time.

          Why EUV Is So Difficult []

          As it turns out, EUV is more difficult to master than previously thought. In fact, it’s arguably the most complex piece of machinery in the history of the IC industry.

          In EUV, a power source converts plasma into light at 13.5nm wavelengths. Then the light bounces off several mirrors before hitting the wafer. Today, EUV can print tiny features on a wafer, but the big problem is the power source—it doesn’t generate enough power to enable an EUV scanner go fast enough or make it economically feasible. In fact, there have been several delays with the source, causing EUV to get pushed out from one node to the next.

          The tide is slowly turning, however. In fact, the confidence level is gradually increasing for EUV in the industry, according to a recent survey from the eBeam Initiative. Moreover, ASML, the sole supplier of EUV scanners, is making progress with the power source. The EUV resists and masks are also improving. But issues remain involving tool costs, uptime and so-called stochastic phenomena.

          All told, EUV is expected to be ready for mass production by 2018 or 2019. If that happens, the industry must get its arms around the technology. But it also must be prepared if EUV stumbles again, which is also possible.

          [SIG] 10/28/2017: Soylent Upgrade v14 []
  • (Score: 0) by Anonymous Coward on Thursday March 30 2017, @08:08PM (2 children)

    by Anonymous Coward on Thursday March 30 2017, @08:08PM (#486715)

    Hyper just sounds so... average these days. We need invent a new word for Intel to name its next incremental variation on x86.

    • (Score: 3, Insightful) by tibman on Thursday March 30 2017, @08:12PM (1 child)

      by tibman (134) Subscriber Badge on Thursday March 30 2017, @08:12PM (#486717)

      ludicrous? plaid?

      SN won't survive on lurkers alone. Write comments.
      • (Score: 0) by Anonymous Coward on Friday March 31 2017, @03:36AM

        by Anonymous Coward on Friday March 31 2017, @03:36AM (#486912)


  • (Score: 2) by inertnet on Thursday March 30 2017, @10:13PM

    by inertnet (4071) on Thursday March 30 2017, @10:13PM (#486777) Journal

    Machines for the production of 10nm chips are being developed here in the Netherlands: []