from the More-Moore? dept.
ARM has announced two new CPU cores, the Cortex-A75 and Cortex-A55. According to ARM, the A75 increases performance by around 22% over the A73 at the same level of power consumption. It can also scale to use more power per core (1-2 W rather than 0.75 W) which could slightly improve the performance of ARM laptops and tablets.
The smaller core, the Cortex-A55, increases performance by around 18% compared to the Cortex-A53, but also increases power consumption by 3%. Thus, power efficiency is about 14-15% better than the A53.
ARM's successor to big.LITTLE, DynamIQ, allows for up to 8 cores of any size (which for now means either the A75 or A55) inside of a single cluster. This means that a configuration including 1x Cortex-A75 and 7x Cortex-A55 cores would be possible, or even optimal according to ARM.
ARM says that the Mali-G72 will see a 25 percent boost to energy efficiency compared with the G71, meaning that SoC designers will have more power to play with to boost performance or increase battery life.
Similarly, the G72 offers 20 percent better performance density, meaning that manufacturers can pack more GPU cores into the same die area as before, giving further potential for a performance boost without an increase in cost. Previously ARM was targeting 16 to 20 Mali-G71 cores as the optimum for mobile, and expects to see the number push closer to the 32 shader core maximum supported by the G72 this time around.
ARM will replace the big.LITTLE cluster design with a new one that allows up to 8 CPU cores per cluster, different types of cores within a cluster, and anywhere from one to many (unlimited?) clusters:
The first stage of DynamIQ is a larger cluster paradigm - which means up to eight cores per cluster. But in a twist, there can be a variable core design within a cluster. Those eight cores could be different cores entirely, from different ARM Cortex-A families in different configurations.
Many questions come up here, such as how the cache hierarchy will allow threads to migrate between cores within a cluster (perhaps similar to how threads migrate between clusters on big.Little today), even when cores have different cache arrangements. ARM did not yet go into that level of detail, however we were told that more information will be provided in the coming months.
Each variable core-configuration cluster will be a part of a new fabric, with uses additional power saving modes and aims to provide much lower latency. The underlying design also allows each core to be controlled independently for voltage and frequency, as well as sleep states. Based on the slide diagrams, various other IP blocks, such as accelerators, should be able to be plugged into this fabric and benefit from that low latency. ARM quoted elements such as safety critical automotive decisions can benefit from this.
A tri-cluster smartphone design using 2 high-end cores, 2 mid-level cores, and 4 low-power cores could be replaced by one that uses all three types of core in the same single cluster. The advantage of that approach remains to be seen.
More about ARM big.LITTLE.