Samsung has added a so-called "4nm" process to its roadmap:
At the annual Samsung Foundry Forum, Samsung announced its foundry's roadmap for the next few years, which includes an 18nm FD-SOI [(Fully Depleted – Silicon on Insulator)] generation targeting low-cost IoT chips as well as 8nm, 7nm, 6nm, 5nm, and even 4nm process generations.
[...] 7LPP (7nm Low Power Plus): 7LPP will be the first semiconductor process technology to use an EUV lithography solution. 250W of maximum EUV source power, which is the most important milestone for EUV insertion into high volume production, was developed by the collaborative efforts of Samsung and ASML. EUV lithography deployment will break the barriers of Moore's law scaling, paving the way for single nanometer semiconductor technology generations.
[...] The 4LPP process generation will be Samsung's first to use a "Gate All Around FET" (GAAFET) transistor structure, with Samsung's own implementation dubbed "Multi Bridge Channel FET" (MBCFET). The technology uses a "Nanosheet" device to overcome the physical limitations of the FinFET architecture.
But how many transistors per square millimeter is it?
Related Stories
Intel is talking about improvements it has made to transistor scaling for the 10nm process node, and claims that its version of 10nm will increase transistor density by 2.7x rather than doubling it.
On the face of it, three years between process shrinks, rather than the traditional two years, would appear to end Moore's Law. But Intel claims that's not so. The company says that the 14nm and 10nm process shrinks in particular more than doubled the transistor density. At 10nm, for example, the company names a couple of techniques that are enabling this "hyperscaling." Each logic cell (an arrangement of transistors to form a specific logic gate, such as a NAND gate or a flip flop) is surrounded by dummy gates: spacers to isolate one cell from its neighbor. Traditionally, two dummy gates have been used at the boundary of each cell; at 10nm, Intel is reducing this to a single dummy gate, thereby reducing the space occupied by each cell and allowing them to be packed more tightly.
Each gate has a number of contacts used to join them to the metal layers of the chip. Traditionally, the contact was offset from the gate. At 10nm, Intel is stacking the contacts on top of the gates, which it calls "contact over active gate." Again, this reduces the space each gate takes, increasing the transistor density.
IBM, which demonstrated the world's first 7nm process silicon chip in 2015, has followed up at the 5nm node. Extreme ultraviolet lithography was required:
IBM, working with Samsung and GlobalFoundries, has unveiled the world's first 5nm silicon chip. Beyond the usual power, performance, and density improvement from moving to smaller transistors, the 5nm IBM chip is notable for being one of the first to use horizontal gate-all-around (GAA) transistors, and the first real use of extreme ultraviolet (EUV) lithography.
GAAFETs are the next evolution of tri-gate finFETs: finFETs, which are currently used for most 22nm-and-below chip designs, will probably run out of steam at around 7nm; GAAFETs may go all the way down to 3nm, especially when combined with EUV. No one really knows what comes after 3nm.
[...] One major advantage of IBM's 5nm GAAFETs is a significant reduction in patterning complexity. Ever since we crossed the 28nm node, chips have become increasingly expensive to manufacture, due to the added complexity of fabricating ever-smaller features at ever-increasing densities. Patterning is the multi-stage process where the layout of the chip—defining where the nanosheets and other components will eventually be built—is etched using a lithographic process. As features get smaller and more complex, more patterning stages are required, which drives up the cost and time of producing each wafer.
[...] IBM says that, compared to commercial 10nm chips (presumably Samsung's 10nm process), the new 5nm tech offers a 40 percent performance boost at the same power, or a 75 percent drop in power consumption at the same performance. Density is also through the roof, with IBM claiming it can squeeze up to 30 billion transistors onto a 50-square-millimetre chip (roughly the size of a fingernail), up from 20 billion transistors on a similarly-sized 7nm chip.
Press release. Also at The Verge, TechCrunch, EE Times, PCMag, and CNET.
Related:
Samsung Plans a "4nm" Process
Taiwan Semiconductor Manufacturing Company (TSMC) plans to make so-called "5nm" chips starting in early 2020:
TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC's 5 nm process starting from early 2020. When all three phases of the manufacturing facility are completed, its wafer starts capacity will exceed one million 300-mm wafers per year, comparable with other three GigaFabs operated by TSMC.
TSMC's Fab 18 will be located in Tainan (in the Southern Taiwan Science Park), and will be built in three phases. The construction of the first phase or segment of the building will be completed in about a year from now, after which TSMC will move in equipment sometime in early 2019. In about two years from now, the company expects to start volume production of chips using its 5 nm process technology at the Fab 18/phase 1. Construction of the second and the third phases will commence in Q3 2018 and Q3 2019. The two phases will start volume production in 2020 and 2021, respectively.
Extreme ultraviolet (EUV) lithography could be used to make "7nm" chips, but not "5nm" yet.
Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
Imec and Cadence Tape Out Industry's First 3nm Test Chip
The world-leading research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. today announced that its extensive, long-standing collaboration has resulted in the industry's first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.
A tape-out is the final step before the design is sent to be fabricated.
Meanwhile, Imec is looking towards nodes smaller than "3nm":
[...] industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, according to the International Technology Roadmap for Semiconductors (ITRS) version 2.0. Another organization, Imec, is more aggressive with the timetable, saying that 2.5nm or thereabouts will arrive by 2024.
Also at EE Times.
Related: TSMC Plans New Fab for 3nm
Samsung Plans a "4nm" Process
IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
Samsung Preps to Build Another Multi-Billion Dollar Memory Fab Near Pyeongtaek
Samsung has begun preparations to build another semiconductor production facility near Pyeongtaek, South Korea. The fab will produce various types of memory as the market demands, and if unofficial information is correct, the new fab may be larger than the adjacent fab that began operations last year.
At present the upcoming fab is called the P2 Project and it will be located adjacent to the existing fab near Pyeongtaek. Samsung has already started to establish infrastructure for the production facility — it ordered the construction of gas pipes for the new production facility in January and is expected to start other works shortly. ETNews reports that Samsung is looking at investing ₩30 trillion ($27.8 billion) in the new P2 Project facility, but does not elaborate whether the number represents total investments, or initial investments. ₩30 trillion is the total amount of money that Samsung has already invested and plans to invest in its existing fab near Pyeongtaek by 2021. Considering the fact that the P2 is in an early stage of planning, it is unlikely that the company has finalized its investments plans.
Related: Samsung Set to Outpace Intel in Semiconductor Revenues
Samsung Could Boost NAND Production Capacity, WD Intervenes in Toshiba Memory Sale
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
Samsung's Second Generation 10nm-Class DRAM in Production
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
Samsung has replaced planned "6nm" and "5nm" nodes with a new "5nm" node on its roadmap, and plans to continue scaling down to "3nm", which will use gate-all-around transistors instead of Fin Field-effect transistors. Extreme ultraviolet lithography (EUV) will be required for everything below "7nm" (TSMC and GlobalFoundries will start producing "7nm" chips without EUV initially):
Last year Samsung said that its 7LPP manufacturing technology will be followed up by 5LPP and 6LPP in 2019 (risk production). The new roadmap does not mention either processes, but introduces the 5LPE (5 nm low power early) that promises to "allow greater area scaling and ultra-low power benefits" when compared to 7LPP. It is unclear when Samsung plans to start using 5LPE for commercial products, but since it is set to replace 7LPP, expect the tech to be ready for risk production in 2019.
[...] Samsung will have two 4 nm process technologies instead of one — 4LPE and 4LPP. Both will be based on proven FinFETs and usage of this transistor structure is expected to allow timely ramp-up to the stable yield level. Meanwhile, the manufacturer claims that their 4 nm nodes will enable higher performance and geometry scaling when compared to the 5LPE, but is not elaborating beyond that (in fact, even the key differences between the three technologies are unclear). Furthermore, Samsung claims that 4LPE/4LPP will enable easy migration from 5LPE, but is not providing any details.
[...] The most advanced process technologies that Samsung announced this week are the 3GAAE/GAAP (3nm gate-all-around early/plus). Both will rely on Samsung's own GAAFET implementation that the company calls MBCFET (multi-bridge-channel FETs), but again, Samsung is not elaborating on any details. The only thing that it does say is that the MBCFET has been in development since 2002, so it will have taken the tech at least twenty years to get from an early concept to production.
MBCFETs are intended to enable Samsung to continue increasing transistor density while reducing power consumption and increasing the performance of its SoCs. Since the 3GAAE/GAAP technologies are three or four generations away, it is hard to make predictions about their actual benefits. What is safe to say is that the 3GAAE will be Samsung's fifth-generation EUV process technology and therefore will extensively use appropriate tools. Therefore, the success of the[sic] EUV in general will have a clear impact on Samsung's technologies several years down the road.
Previously: Samsung Plans a "4nm" Process
Related: IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
Samsung is preparing to manufacture 7LPP and 5LPE process ARM chips:
Samsung has said its chip foundry building Arm Cortex-A76-based processors will use 7nm process tech in the second half of the year, with 5nm product expected mid-2019 using the extreme ultra violet (EUV) lithography process.
The A76 64-bit chips will be able to pass 3GHz in clock speed. Back in May we wrote: "Arm reckoned a 3GHz 7nm A76 single core is up to 35 per cent faster than a 2.8GHz 10nm Cortex-A75, as found in Qualcomm's Snapdragon 845, when running mixed integer and floating-point math benchmarks albeit in a simulator."
[...] Samsung eventually envisages moving to a 3nm Gate-All-Round-Early (3AAE) on its process technology roadmap. Catch up, Intel, if you can.
Also at AnandTech.
Previously: Samsung Roadmap Includes "5nm", "4nm" and "3nm" Manufacturing Nodes
Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap (obsolete)
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process
(Score: 2) by kaszz on Sunday June 04 2017, @12:50PM (2 children)
Intel has been beaten?
Samsung made AMD-x86 or ARM.. in 4 nm. Maybe that would be something?
(Score: 2) by mth on Sunday June 04 2017, @01:47PM (1 child)
Samsung already makes ARM SoCs: Exynos [wikipedia.org]. They're not a threat to Intel in terms of absolute performance, but when it comes to power efficiency ARM chips have been ahead of Intel for a long time.
(Score: 2) by kaszz on Sunday June 04 2017, @02:09PM
My point is that with processor manufactured in a 4 nm process those might perhaps beat Intel in speed and power efficiency?
That the ARM architecture is more efficient than Intel is of course not news.
(Score: 0) by Anonymous Coward on Sunday June 04 2017, @02:05PM (1 child)
> 250W of maximum EUV source power
According to https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithography [wikipedia.org] , making extreme UV is extremely inefficient --
> Xe or Sn plasma sources are either discharge-produced or laser-produced. Discharge-produced plasma is made by discharging a lightning bolt's worth of electric current through a tin vapor. Laser-produced plasma is made by microscopic droplets of molten tin heated by powerful laser. Laser-produced plasma sources (e.g., ASML's NXE:3300B scanner) outperform discharge-produced plasma sources. Power output exceeding 250 W is a requirement for sufficient throughput.
>
> While state-of-the-art 193 nm ArF excimer lasers offer intensities of 200 W/cm2,[32] lasers for producing EUV-generating plasmas need to be much more intense, on the order of 1011 W/cm2.[33] This indicates the enormous energy burden imposed by switching from 193 nm light (power output approaching 100 W)[34] to EUV light (10 kW).[35] An EUV source driven by a 200 kW CO2 laser with ~10% wall plug efficiency[36] consumes an electrical power of ~2 MW, while a 100 W ArF immersion laser with ~1% wall plug efficiency[37] consumes an electrical power of ~10 kW. A state-of-the-art ArF immersion lithography 120 W light source requires no more than 40 kW[38] while EUV sources are targeted to exceed 40 kW.[39]
(Score: 0) by Anonymous Coward on Sunday June 04 2017, @11:07PM
So, will the power saving from smaller chip features exceed the extreme amount of power used by EUV during manufacture? I don't know enough to do the envelope calculation, anyone have a clue? 2MW is a lot of power, and a wafer goes through weeks of process steps.
Car analogy -- Like payback on a Prius, eventually the extra first cost is recouped in fuel savings, as long as you drive enough miles and the price of gasoline is high enough.
(Score: 2) by FatPhil on Sunday June 04 2017, @07:02PM (6 children)
Moore's law, when used as a predictive statement, indicates that the number of transistors that will fit on a die will grow exponentially. It has therefore been used to predict that there will be *no barriers*. (Not that it was intended to be a long-term predictive statement, and the teenies and twenties can definitely be considered the distant future of when it was made.)
Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves
(Score: -1, Flamebait) by Anonymous Coward on Sunday June 04 2017, @08:01PM
Seriously, just fuck off.
(Score: 2) by takyon on Sunday June 04 2017, @08:12PM (2 children)
Nitpick-tier complaint.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 3, Interesting) by FatPhil on Sunday June 04 2017, @08:27PM (1 child)
Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves
(Score: 3, Informative) by takyon on Sunday June 04 2017, @08:48PM
There have always been barriers to further scaling. Whether they can be overcome or not, or overcome economically, are other concerns.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by martyb on Monday June 05 2017, @07:08AM (1 child)
Close, but not quite. This is a commonly-repeated but misunderstood aspect of Moore's Law. It was not just about exponential growth. Gordon Moore made a prediction regarding the number of transistors that could be produced at minimum cost.
Refer to "PROCEEDINGS OF THE IEEE, VOL. 86, NO. 1, JANUARY 1998 [utexas.edu] (pdf)" which, in turn, stated: "Reprinted from Gordon E. Moore, "Cramming More Components onto Integrated Circuits," Electronics, pp. 114117, April 19, 1965. Publisher Item Identifier S 0018-9219(98)00753-1."
An excerpt follows, with my emphasis added:
The graph herein referenced is presented as "Figure 3" and includes the famous mapping of "Log2 of the number of components per integrated function" (y-axis) versus "date" (x-axis) and which depicts the oft-repeated "doubling of transistors per year". Having already stated in the text his qualification that these would be produced at minimum cost, and given that the text label on the y-axis already encompassed three physical lines in the graph, it is understandable that he did not also include the qualification "at minimum cost" in that label. It seems to me that some people glanced at the plot, saw the pattern, and neglected to read the text. They widely proclaimed their viewpoint (neglecting minimum cost) and eventually that is what people remember, instead of what Gordon Moore actually stated.
The amazing thing, from my perspective, was that "law" was postulated in 1965 which is over FIFTY YEARS AGO! There were no cell phones, laptops, or even personal computers back then. We're talking computers that were minimally the size of refrigerators. Now think of the rate of change in electronics we've witnessed since then. That his "law" (more correctly "observation" -- but that takes too many syllables) has held true for such a long period of time utterly amazes me. Moore made an extrapolation based on a few years' worth of results, when we were basically just getting started with integrated circuits, and it has basically held true for decades!
Now, back to THIS story, my take is based on two things. For better or worse, Samsung is based out of South Korea. I took this phrasing as simply being as an error of translation of an abstract concept. I understood it to mean: "we were approaching roadblocks which blocked our constructing smaller and smaller features.
Visible light has a wavelength on the order of 500nm. Through tremendous feats of engineering, we've witnessed smaller and smaller features continue to roll out. As we step away from visible light into ultra-violet, it is possible to construct finer and finer features. But there are limits with what can be done. Creating those precise frequencies at sufficient power levels to use in photo-lithography was starting to look like a hard barrier. Many were pursuing different approaches that worked in theory, but putting that into practice continued to run into roadblocks. Maybe we HAD reached the end of Moore's Law?
This press release is simply stating that they have found a way to overcome that limitation, that they have a means of using extreme ultra-violet, and that they plan to use that to develop "7nm" feature sizes. (I'll not get into the whole discussion as to what is actually measured when one speaks about, say a 10nm process step or feature size.)
So, I'll grant you that it is not the clearest phrasing, but a little tolerance of a mis-translation to English explains it well enough for me.
Wit is intellect, dancing.
(Score: 2) by FatPhil on Monday June 05 2017, @10:37AM
Because Samsung are a small cash-strapped company who can't afford a proof-reader who is familiar with technology, yeah, right.
I shouldn't be surprised, even the contract I signed with SR-UK (Samsung Research UK) was in pretty mangled English.
Even Moore's English is a bit mangled, I'm sure he's talking about minimum cost per unit of functionality, which isn't the absolute minimum cost. MCUs are typically built on what might be considered very legacy processes (I guess 60-90, but I'm a bit out of touch), but they're not designed to have much functionality at all. Smaller than the smallest package size simply isn't worth it.
Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves