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posted by Fnord666 on Wednesday July 05 2017, @06:21PM   Printer-friendly
from the profit-earnings-ratio dept.

While QLC NAND is predicted to have as low as 100 program/erase cycles (endurance), Toshiba has "targeted" 1000 cycles for its upcoming 3D QLC NAND products:

Toshiba last week announced its first 3D NAND flash memory chips featuring [the] QLC (quadruple level cell) BiCS architecture. The new components feature 64 layers and developers of SSDs and SSD [controllers] have already received samples of the devices, which Toshiba plans to use for various types of storage solutions.

[...] Besides [its] intention to produce 768 Gb 3D QLC NAND flash for the aforementioned devices, the most interesting part of Toshiba's announcement is [the] endurance specification for the upcoming components. According to the company, its 3D QLC NAND is targeted for ~1000 program/erase cycles, which is close to TLC NAND flash. This is considerably higher than the amount of P/E cycles (100 – 150) expected for QLC by the industry over the years. At first thought, it comes across [as] a typo - didn't they mean 100?. But the email we received was quite clear:

- What's the number of P/E cycles supported by Toshiba's QLC NAND?
- QLC P/E is targeted for 1K cycles.

Endurance miracle putting QLC on par with TLC, or idle talk about a product that won't be out for 1-2 years?

[Ed. note: If you're wondering what QLC NAND is, here's a quick primer.]

Additional Coverage: The guru of 3D


Original Submission

Related Stories

Expect 20-30% Cheaper NAND in Late 2018 7 comments

The 512 Gb dies are coming:

64-layer 3D NAND is shipping, but the 256Gbit die will come and go rapidly. That's what makes this NAND cycle different. Many of the companies we've spoken to do not want to invest in products with such a limited shelf life. The 512Gbit die are right around the corner from the fabs. Some estimates put a major ramp up coming before mid year. The technology offers a 2x capacity increase while taking only a little more space on the wafer. The bits per wafer doesn't double, but it gets very close. The retail products coming in the second half of 2018 with have a heavy impact on SSD pricing. Some estimates from engineers we've spoken with put retail pricing on track for a 20% to 30% reduction over similar-capacity products shipping today.

Emerging technologies and form factors that reduce the material costs will also play a role. Toshiba Memory America showcased the new RC100 NVMe SSD that uses multi-chip packaging to cram the controller and flash in a single package.

Toshiba has described stacking 8-16 512 Gb dies with through silicon vias (TSVs) to create 512 GB and 1 TB packages. Samsung plans to stack 32 256 Gb dies to make 1 TB packages for an upcoming 128 TB SSD.

Previously: SK Hynix Plans 72-Layer 512 Gb NAND for Late 2017
SK Hynix Developing 96 and 128-Layer TLC 3D NAND
Intel First to Market With 64-Layer 3D NAND SSDs
Western Digital Announces 96-Layer 3D NAND, Including Both TLC and QLC
Toshiba's 3D QLC NAND Could Reach 1000 P/E Cycles
WD Announces 64-Layer 3D QLC NAND With 768 Gb Per Die, to be Shown at Flash Memory Summit


Original Submission

WD Announces 64-Layer 3D QLC NAND With 768 Gb Per Die, to be Shown at Flash Memory Summit

Both Toshiba (or whomever ends up buying Toshiba's memory fabrication assets) and Western Digital (WD) have both recently announced plans to produce 3D QLC (four bits per cell) NAND:

Western Digital's SanDisk subsidiary and Toshiba have a long history of jointly developing and manufacturing NAND flash memory. While that relationship has been strained by Toshiba's recent financial troubles and attempts to sell of their share of the memory business, the companies are continuing to develop new flash memory technology and are still taking turns making new announcements. In recent months both companies have started sampling SSDs using their 64-layer BiCS3 TLC 3D NAND and have announced that their next generation BiCS4 3D NAND will be a 96-layer design.

Yesterday Western Digital made a small announcement about their other main strategy for increasing density: storing more bits per memory cell. Western Digital will introduce four bit per cell QLC parts built on their 64-layer BiCS3 process, with a capacity of 768Gb (96GB) per die. This is a substantial increase over the 512Gb BiCS3 TLC parts that will be hitting the market soon, and represents not only an increase in in bits stored per memory cell but an increase in the overall size of the memory array. These new 3D QLC NAND parts are clearly intended to offer the best price per GB that Western Digital can manage, but Western Digital claims performance will still be close to that of their 3D TLC NAND. Western Digital's announcement did not mention write endurance, but Toshiba's earlier announcement of 3D QLC NAND claimed endurance of 1000 program/erase cycles, far higher than industry expectations of 100-150 P/E cycles for 3D QLC and comparable to 3D TLC NAND.

Western Digital will showcase SSDs and removable flash media using QLC NAND at the Flash Memory Summit from August 8-10.

Will QLC NAND endurance become a bigger issue than it is with TLC? Will this be used primarily for high density cold storage like Facebook has asked for?

Previously: Toshiba Teasing QLC 3D NAND and TSV for More Layers
SK Hynix Developing 96 and 128-Layer TLC 3D NAND
Western Digital Announces 96-Layer 3D NAND, Including Both TLC and QLC
Toshiba's 3D QLC NAND Could Reach 1000 P/E Cycles
Toshiba Develops 512 GB and 1 TB Flash Chips Using TSV


Original Submission

Toshiba Develops 512 GB and 1 TB Flash Chips Using TSV 9 comments

While other manufacturers are making 512 Gb to 1 Tb 3D NAND flash dies, Toshiba is using through-silicon vias (TSVs) to stack their dies, effectively cramming 384 to 768 layers of 3D NAND into a single chip. Toshiba announced that it was developing this capability back in 2015, and now the first products to use it will be available in 2018:

Toshiba on Wednesday introduced its first BiCS 3D TLC NAND flash chips with 512 GB and 1 TB capacities. . The new ICs stack 8 or 16 3D NAND devices using through silicon vias (TSVs) and are currently among the highest capacity non-volatile memory stacks available in the industry. Commercial products powered by the 512 GB and 1 TB packages are expected to hit the market in 2018, with an initial market focus on high-end enterprise SSDs

Stacking NAND devices to build high capacity flash memory ICs has been used for years to maximize the capacities and performance of SSDs and other solid state storage devices. In many cases, NAND makers use wire-bonding technique to stack multiple memory devices, but it makes packages larger and requires a lot of power for reliable operation. However in more recent years, Toshiba has adopted TSV techniques previously used for ASIC and DRAM devices to stack its NAND ICs, which has enabled it to shrink size of its NAND packages and reduce their power consumption.

TSVs are essentially electrodes that penetrate the entire thickness of a silicon die and connect the dies above and below it in the stack. A bus formed by TSVs can operate at a high data transfer rate, consume less power, and take up less space than a bus made using physical wires. Since 3D NAND is based on vertically stacked memory layers and has numerous vertical interconnects, so far Toshiba has not used TSVs to interconnect such devices. To wed TSV and 3D NAND, Toshiba had to develop a special 512 Gb BiCS NAND die featuring appropriate electrical conductors.

The devices both measure 14 mm × 18 mm. The 8-stack chip has a height of 1.35 mm, and the 16-stack chip has a height of 1.85 mm.

Toshiba press release.

Western Digital Announces 96-Layer 3D NAND, Including Both TLC and QLC 2 comments

Western Digital has announced that it will begin production of 96-layer 3D NAND in 2018. It will make triple-level cell and quad-level cell NAND with die capacities ranging from 256 Gb to 1 Tb. QLC NAND is predicted to have 100-150 program/erase cycles (endurance) compared to about 1000 for TLC:

Given such endurance, it is logical to expect 3D QLC NAND to be used for primarily removable storage as well as for ultra-high capacity datacenter drives for the so-called near-WORM (write once read many) storage applications. For example, Toshiba last year discussed a QLC-based datacenter SSD with 100 TB capacity for WORM apps.

Western Digital plans to begin sampling of select 96-layer BiCS4 3D NAND configurations in the second half of this year, but the manufacturer does not specify which dies will sample when. As for mass production, Western Digital intends to start volume manufacturing of their 96-layer 256 Gb 3D NAND in 2018, with other dies to follow later. Based on Western Digital's announcements made earlier, the company will gradually introduce more sophisticated BiCS4 96-layer configurations in 2018 and 2019, before moving to BiCS5 sometimes in 2020. That said, it makes sense to expect the highest capacity BiCS4 ICs to ship later rather than sooner.

[BiCS = "Bit-Cost Scaling". Yes, it does not make sense to me, either. --Ed.]


Original Submission

Samsung Announces a 128 TB SSD With QLC NAND 9 comments

Samsung will use QLC NAND to create a 128 TB SSD:

For now, let's talk about the goods we'll see over the next year. The biggest news to come out of the new Samsung campus is QLC flash. Samsung's customers set performance and endurance specifications and don't care about the underlying technology as long as those needs are met. Samsung says it can achieve its targets with its first generation QLC (4-bits per cell) V-NAND technology.

The first product pre-announcement (it doesn't have a product number yet) is a 128TB SAS SSD using QLC technology with a 1TB die size. The company plans to go beyond 16 die per package using chip stacking technology that will yield 32 die per package, a flash industry record.

NAND revenue has increased 55% in one year.

Previously: Seagate Demonstrates a 60 TB 3.5" SSD
Toshiba Envisions a 100 TB QLC SSD in the "Near Future"
Western Digital Announces 96-Layer 3D NAND, Including Both TLC and QLC
Toshiba's 3D QLC NAND Could Reach 1000 P/E Cycles


Original Submission

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  • (Score: 4, Insightful) by kaszz on Wednesday July 05 2017, @07:08PM (6 children)

    by kaszz (4211) on Wednesday July 05 2017, @07:08PM (#535354) Journal

    Regular EEPROM is on the order of 100 000 writes and 10 years retention. A memory used as secondary storage "disc" ought to have way more write cycles to be viable.

    Maybe I'm missing something fundamental here. But currently this memory seems to fit the role of a mostly read only cache for often used data and boot code.

    • (Score: 3, Informative) by takyon on Wednesday July 05 2017, @07:27PM

      by takyon (881) Subscriber Badge <reversethis-{gro ... s} {ta} {noykat}> on Wednesday July 05 2017, @07:27PM (#535369) Journal

      There are numerous 3D TLC NAND SSDs out there. Typical warranty for TLC seems to be three [tomsitpro.com] years [anandtech.com]. If QLC NAND can somehow match the endurance of TLC, then it could work just fine.

      The massive capacity of 3D NAND SSDs can allow for overprovisioning to keep the capacity usable.

      If you don't need multiple drive writes per day, or if you treat it like write-once-read-many "cold storage", then there won't necessarily be a problem. Capacity/$ is what is desired for this storage tier, not stellar endurance.

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    • (Score: 2) by fnj on Thursday July 06 2017, @04:26PM (4 children)

      by fnj (1654) on Thursday July 06 2017, @04:26PM (#535772)

      Five years ago they already knew how to make NAND flash with at least 100 MILLION P/E cycles [ieee.org]! What the hell happened to that tech?

      • (Score: 2) by takyon on Thursday July 06 2017, @06:10PM (3 children)

        by takyon (881) Subscriber Badge <reversethis-{gro ... s} {ta} {noykat}> on Thursday July 06 2017, @06:10PM (#535810) Journal

        It was probably too expensive and became abandoned once 3D/vertical NAND eliminated the "endurance wall".

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        • (Score: 2) by kaszz on Thursday July 06 2017, @09:35PM (2 children)

          by kaszz (4211) on Thursday July 06 2017, @09:35PM (#535889) Journal

          How can vertical NAND eliminate a 100 write limit? that is like 4 magnitudes worse performance..

          • (Score: 2) by takyon on Thursday July 06 2017, @10:08PM (1 child)

            by takyon (881) Subscriber Badge <reversethis-{gro ... s} {ta} {noykat}> on Thursday July 06 2017, @10:08PM (#535906) Journal

            http://www.anandtech.com/show/8239/update-on-samsung-850-pro-endurance-vnand-die-size [anandtech.com]

            http://www.tomsitpro.com/articles/samsung-pm863-3d-tlc-v-nand-ssd,2-958.html [tomsitpro.com]

            3D NAND steps back to a larger lithography than its planar counterparts do, which imparts enough endurance to ensure that 3D TLC NAND is a reliable solution.

            Also overprovisioning [kingston.com] which there is more room to do with vertical.

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            • (Score: 2) by kaszz on Saturday July 08 2017, @02:40AM

              by kaszz (4211) on Saturday July 08 2017, @02:40AM (#536378) Journal

              The explanation on how they succeed with real life re-write endurance when looking past the overprovisioning is still not explained. The closest I have read is some Taiwanese engineers coming up with a heating method to make bad cells anneal and accomplish 100 million re-write performance.

              In the end it seems these kinds of memories are good for some specific use cases. Mechanical harddiscs still have a major durability advantage. Laptops may be a special case. But reliance on electrical charge + gamma scanners at airports or electrical disruptive environments seems risky. And when they crash it's a hard one.

  • (Score: 3, Interesting) by Azuma Hazuki on Thursday July 06 2017, @12:52AM (1 child)

    by Azuma Hazuki (5086) Subscriber Badge on Thursday July 06 2017, @12:52AM (#535483) Journal

    ...and THAT is cemented to the floor. And even if they DO get 1K P/E cycles out of this, what about storage? Remember that the number of states a cell has to be able to encode varies as 2^X where X is how many "levels" the cell has. It takes a lot less electron migration to go from 1111 to 1110 (QLC, 2^4 or 16) than it does to go from 111 to 110 (TLC, 2^3 or 8), which in turn takes less than to go from 11 to 10 (MLC, 2^2 or 4), and less still than 1 to 0 (SLC, 2^1 or 2).

    This is why I'm sceptical of the "great for archive/low-write loads!" claim. Especially if they're all packed together like herring in the barrel in some hot 2U rack somewhere.

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  • (Score: 2) by realDonaldTrump on Thursday July 06 2017, @01:12PM

    by realDonaldTrump (6614) Subscriber Badge on Thursday July 06 2017, @01:12PM (#535700) Homepage Journal

    It used to be, you wanted some water, they brought it in a glass. You drink your water, they want the glass back. They wash it and they use it again. Over and over. Now we have bottles, we have the plastic bottles. You drink your water, you throw away the bottle, that's the end of it. It's disposable. And somebody makes a lot, a lot of money selling the bottles. It used to be, you used a rubber, you washed it, dried it and used it again. Over and over (I had a guy to wash mine). Now, you use it and you throw it away. And somebody makes a lot of money, a lot more money, selling the rubbers. Now they have disposable cyber. You use it, you throw it away, that's the end of it. And somebody makes a lot of money selling the cyber. Very smart move! 🇺🇸

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