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posted by martyb on Wednesday July 19 2017, @03:29PM   Printer-friendly
from the quite-a-bit-of-an-improvement dept.

While other manufacturers are making 512 Gb to 1 Tb 3D NAND flash dies, Toshiba is using through-silicon vias (TSVs) to stack their dies, effectively cramming 384 to 768 layers of 3D NAND into a single chip. Toshiba announced that it was developing this capability back in 2015, and now the first products to use it will be available in 2018:

Toshiba on Wednesday introduced its first BiCS 3D TLC NAND flash chips with 512 GB and 1 TB capacities. . The new ICs stack 8 or 16 3D NAND devices using through silicon vias (TSVs) and are currently among the highest capacity non-volatile memory stacks available in the industry. Commercial products powered by the 512 GB and 1 TB packages are expected to hit the market in 2018, with an initial market focus on high-end enterprise SSDs

Stacking NAND devices to build high capacity flash memory ICs has been used for years to maximize the capacities and performance of SSDs and other solid state storage devices. In many cases, NAND makers use wire-bonding technique to stack multiple memory devices, but it makes packages larger and requires a lot of power for reliable operation. However in more recent years, Toshiba has adopted TSV techniques previously used for ASIC and DRAM devices to stack its NAND ICs, which has enabled it to shrink size of its NAND packages and reduce their power consumption.

TSVs are essentially electrodes that penetrate the entire thickness of a silicon die and connect the dies above and below it in the stack. A bus formed by TSVs can operate at a high data transfer rate, consume less power, and take up less space than a bus made using physical wires. Since 3D NAND is based on vertically stacked memory layers and has numerous vertical interconnects, so far Toshiba has not used TSVs to interconnect such devices. To wed TSV and 3D NAND, Toshiba had to develop a special 512 Gb BiCS NAND die featuring appropriate electrical conductors.

The devices both measure 14 mm × 18 mm. The 8-stack chip has a height of 1.35 mm, and the 16-stack chip has a height of 1.85 mm.

Toshiba press release.

Related Stories

Toshiba Brings Through-Silicon Vias to NAND Flash 15 comments

Toshiba has showed off a NAND flash device using through-silicon vias (TSVs) to stack 16 NAND dies, a technology it announced earlier this month. From Tom's Hardware:

TSV technology removed the wire bonding from the edges of the die. Instead, the signal is passed through the entire stack vertically. Vertical NAND, often referred to as V-NAND or 3D NAND, differs from TSV, though. Nothing leads us to believe that the two technologies can't work together, but at this time we are unaware of any designs that merge the two technologies.

[...] Toshiba's partners are excited about this product for two reasons: The first is performance. PMC Sierra makes very high-performing NVMe SSDs that move the bottleneck from the PCIe interface to the flash itself. The Princeton controller uses 32 channels to address a large number of flash die and is a very expensive controller to manufacture. If the company is able to reach the same performance level with just 16 channels, the overall cost will drop. The capacity can remain the same because TSV allows Toshiba to stack twice the number of die in each package.

Performance is only one aspect of the overall datacenter equation, though. The upfront costs are minimal compared to the long term costs due to power consumption. PMC Sierra demonstrated a very wide gap in power efficiency between non-TSV Toggle mode flash and new TSV Toggle mode flash.

The use of TSV could help scale NAND capacity in the vertical dimension even further.


Original Submission

Western Digital and Samsung at the Flash Memory Summit 11 comments

Western Digital has announced its intention to include 3D Resistive RAM (ReRAM) as storage class memory (SCM) in future SSDs and other products:

Without making any significant announcements this week, Western Digital indicated that it would use some of the things it has learnt while developing its BiCS 3D NAND to produce its ReRAM chips. The company claims that its ReRAM will feature a multi-layer cross-point implementation, something it originally revealed a while ago.

Perhaps, the most important announcement regarding the 3D ReRAM by Western Digital is the claim about scale and capital efficiency of the new memory. Essentially, this could mean that the company plans to use its manufacturing capacities as well as its infrastructure (testing, packaging, etc.) in Yokkaichi, Japan, to make 3D ReRAM. Remember that SCM is at this point more expensive than NAND, hence, it makes sense to continue using the current fabs and equipment to build both types of non-volatile memory so ensure that the SCM part of the business remains profitable.

One of WD's slides projects SCM as 50% the cost per gigabyte of DRAM in 2017, declining to 5% by 2023.

Samsung introduced its fourth generation of vertical NAND, with 64 layers:

With a per-die capacity of 512Gb (64GB), Samsung can now put 1TB of TLC flash in a single package. This means most product lines will be seeing an increase in capacity at the high end of the range. Their BGA SSD products will be offering 1TB capacity even in the 11.5mm by 13mm form factor. The 16TB PM1633a SAS SSD will be eclipsed by the new 32TB PM1643. Likely to be further out, the PM1725 PCIe add-in card SSD will be succeeded by the PM1735 with a PCIe 4 x8 host interface.

Complementing the NAND update will be a new non-standard oversized M.2 form factor 32mm wide and 114mm long, compared to the typical enterprise M.2 size of 22mm by 110mm. A little extra room can go a long way, and Samsung will be using it to produce 8TB drives. These will be enterprise SSDs and Samsung showed a diagram of these enabling 256TB of flash in a 1U server. Samsung will also be producing 4TB drives in standard M.2 sizing.

In what is likely a bid to steal some thunder from 3D XPoint memory before it can ship, Samsung announced Z-NAND memory technology and a Z-SSD product based around Z-NAND and a new SSD controller. They said nothing about the operating principles of Z-NAND, but they did talk about their plans for the Z-SSD products.


Original Submission

SK Hynix Plans 72-Layer 512 Gb NAND for Late 2017 5 comments

Samsung recently announced its fourth generation of 3D/vertical NAND, with 64 layers and a capacity of 512Gb (64GB) per die. Now SK Hynix is announcing its plans for 512 Gb V-NAND dies with 72 layers:

Later this year SK Hynix intends to start volume production of 72-layer 3D TLC NAND (3D-V4) memory and this is where things start to get interesting. Initially, SK Hynix intends to produce 256 Gb 3D TLC ICs and these are going to be available already in Q2 2017, according to the company's product catalog. Later on, sometimes in Q4, the company plans to introduce 512 Gb 3D TLC ICs (64 GB), which will help it to significantly increase capacities of SSDs and other devices featuring NAND flash.

What is important about SK Hynix's fourth-gen 3D NAND is that it will feature block size of 13.5 MB, which will increase the performance of such ICs compared to 3D-V3 and 3D-V2 that have a block size of 9 MB. At this point, we do not know whether SK Hynix intends to increase interface speed of its 512 Gb 3D-V4 ICs to compensate lower parallelism in lower-capacity SSDs, like Samsung did with its high-capacity 64-layer 3D V-NAND chips. What we do know is that SK Hynix's catalog already includes NAND multi-chip packages of 8192 Gb capacity (1 TB) that will enable high-capacity SSDs in smaller form-factors (e.g., [2 TB] single-sided M.2). Meanwhile, 64 GB NAND flash chips may force SK Hynix and its partners to abandon low-capacity SSDs (i.e., 120/128 GB) unless there is sufficient demand.

The article also talks about the company's plans for 18nm DRAM and fabrication facility expansion.

Related: Toshiba and SanDisk Announce 48-Layer 256 Gb 3D NAND
Toshiba Teasing QLC 3D NAND and TSV for More Layers


Original Submission

SK Hynix Developing 96 and 128-Layer TLC 3D NAND 3 comments

SK Hynix is currently developing 96-layer and 128-layer 3D NAND with 3 bits per cell, but may be skipping quad-level cell 3D NAND for some time:

The 64-layer 3D NAND about to land from Micron and Toshiba certainly sounds impressive, but it pales in comparison to what Sk Hynix is working on for future release. The company is developing 96-layer and 128-layer 3D NAND flash. The new flash won't be available for a few years, but that makes it no less exciting. We have yet to see 72-layer 3D from Sk Hynix in our lab, but it will begin shipping soon in the PC401 using 256Gbit TLC die, according to the UNH-IOL list of tested products.

The information we found about the successor to 256Gbit 72-layer 3D TLC shows 96 layers with 512Gbit die capacity. The follow up to that is a massive 1Tbit die from 128-layer TLC from the other South Korean SSD manufacturer with full vertical integration.

Toshiba (or whichever company acquires Toshiba's memory division) may be more likely to introduce QLC 3D NAND.

Previously:
SK Hynix Plans 72-Layer 512 Gb NAND for Late 2017
64-Layer 3D NAND at Computex


Original Submission

Toshiba's 3D QLC NAND Could Reach 1000 P/E Cycles 10 comments

While QLC NAND is predicted to have as low as 100 program/erase cycles (endurance), Toshiba has "targeted" 1000 cycles for its upcoming 3D QLC NAND products:

Toshiba last week announced its first 3D NAND flash memory chips featuring [the] QLC (quadruple level cell) BiCS architecture. The new components feature 64 layers and developers of SSDs and SSD [controllers] have already received samples of the devices, which Toshiba plans to use for various types of storage solutions.

[...] Besides [its] intention to produce 768 Gb 3D QLC NAND flash for the aforementioned devices, the most interesting part of Toshiba's announcement is [the] endurance specification for the upcoming components. According to the company, its 3D QLC NAND is targeted for ~1000 program/erase cycles, which is close to TLC NAND flash. This is considerably higher than the amount of P/E cycles (100 – 150) expected for QLC by the industry over the years. At first thought, it comes across [as] a typo - didn't they mean 100?. But the email we received was quite clear:

- What's the number of P/E cycles supported by Toshiba's QLC NAND?
- QLC P/E is targeted for 1K cycles.

Endurance miracle putting QLC on par with TLC, or idle talk about a product that won't be out for 1-2 years?

[Ed. note: If you're wondering what QLC NAND is, here's a quick primer.]

Additional Coverage: The guru of 3D


Original Submission

Expect 20-30% Cheaper NAND in Late 2018 7 comments

The 512 Gb dies are coming:

64-layer 3D NAND is shipping, but the 256Gbit die will come and go rapidly. That's what makes this NAND cycle different. Many of the companies we've spoken to do not want to invest in products with such a limited shelf life. The 512Gbit die are right around the corner from the fabs. Some estimates put a major ramp up coming before mid year. The technology offers a 2x capacity increase while taking only a little more space on the wafer. The bits per wafer doesn't double, but it gets very close. The retail products coming in the second half of 2018 with have a heavy impact on SSD pricing. Some estimates from engineers we've spoken with put retail pricing on track for a 20% to 30% reduction over similar-capacity products shipping today.

Emerging technologies and form factors that reduce the material costs will also play a role. Toshiba Memory America showcased the new RC100 NVMe SSD that uses multi-chip packaging to cram the controller and flash in a single package.

Toshiba has described stacking 8-16 512 Gb dies with through silicon vias (TSVs) to create 512 GB and 1 TB packages. Samsung plans to stack 32 256 Gb dies to make 1 TB packages for an upcoming 128 TB SSD.

Previously: SK Hynix Plans 72-Layer 512 Gb NAND for Late 2017
SK Hynix Developing 96 and 128-Layer TLC 3D NAND
Intel First to Market With 64-Layer 3D NAND SSDs
Western Digital Announces 96-Layer 3D NAND, Including Both TLC and QLC
Toshiba's 3D QLC NAND Could Reach 1000 P/E Cycles
WD Announces 64-Layer 3D QLC NAND With 768 Gb Per Die, to be Shown at Flash Memory Summit


Original Submission

WD Announces 64-Layer 3D QLC NAND With 768 Gb Per Die, to be Shown at Flash Memory Summit

Both Toshiba (or whomever ends up buying Toshiba's memory fabrication assets) and Western Digital (WD) have both recently announced plans to produce 3D QLC (four bits per cell) NAND:

Western Digital's SanDisk subsidiary and Toshiba have a long history of jointly developing and manufacturing NAND flash memory. While that relationship has been strained by Toshiba's recent financial troubles and attempts to sell of their share of the memory business, the companies are continuing to develop new flash memory technology and are still taking turns making new announcements. In recent months both companies have started sampling SSDs using their 64-layer BiCS3 TLC 3D NAND and have announced that their next generation BiCS4 3D NAND will be a 96-layer design.

Yesterday Western Digital made a small announcement about their other main strategy for increasing density: storing more bits per memory cell. Western Digital will introduce four bit per cell QLC parts built on their 64-layer BiCS3 process, with a capacity of 768Gb (96GB) per die. This is a substantial increase over the 512Gb BiCS3 TLC parts that will be hitting the market soon, and represents not only an increase in in bits stored per memory cell but an increase in the overall size of the memory array. These new 3D QLC NAND parts are clearly intended to offer the best price per GB that Western Digital can manage, but Western Digital claims performance will still be close to that of their 3D TLC NAND. Western Digital's announcement did not mention write endurance, but Toshiba's earlier announcement of 3D QLC NAND claimed endurance of 1000 program/erase cycles, far higher than industry expectations of 100-150 P/E cycles for 3D QLC and comparable to 3D TLC NAND.

Western Digital will showcase SSDs and removable flash media using QLC NAND at the Flash Memory Summit from August 8-10.

Will QLC NAND endurance become a bigger issue than it is with TLC? Will this be used primarily for high density cold storage like Facebook has asked for?

Previously: Toshiba Teasing QLC 3D NAND and TSV for More Layers
SK Hynix Developing 96 and 128-Layer TLC 3D NAND
Western Digital Announces 96-Layer 3D NAND, Including Both TLC and QLC
Toshiba's 3D QLC NAND Could Reach 1000 P/E Cycles
Toshiba Develops 512 GB and 1 TB Flash Chips Using TSV


Original Submission

Samsung Announces a 30.72 TB 2.5" SSD 15 comments

Samsung has announced a 30.72 TB SSD. It uses 64-layer 512 Gb TLC NAND dies, with 16 of each stacked to make a 1 TB package. It has 40 GB of DDR4 DRAM cache, also using layered packages:

The PM1643 drive also applies Through Silicon Via (TSV) technology to interconnect 8Gb DDR4 chips, creating 10 4GB TSV DRAM packages, totaling 40GB of DRAM. This marks the first time that TSV-applied DRAM has been used in an SSD.

Complementing the SSD's hardware ingenuity is enhanced software that supports metadata protection as well as data retention and recovery from sudden power failures, and an error correction code (ECC) algorithm to ensure high reliability and minimal storage maintenance. Furthermore, the SSD provides a robust endurance level of one full drive write per day (DWPD), which translates into writing 30.72TB of data every day over the five-year warranty period without failure. The PM1643 also offers a mean time between failures (MTBF) of two million hours.

Samsung started manufacturing initial quantities of the 30.72TB SSDs in January and plans to expand the lineup later this year – with 15.36TB, 7.68TB, 3.84TB, 1.92TB, 960GB and 800GB versions – to further drive the growth of all-flash-arrays and accelerate the transition from hard disk drives (HDDs) to SSDs in the enterprise market.

Also at Ars Technica and The Verge.

Related: SK Hynix Plans 72-Layer 512 Gb NAND for Late 2017
SK Hynix Developing 96 and 128-Layer TLC 3D NAND
Western Digital Announces 96-Layer 3D NAND, Including Both TLC and QLC
Toshiba Develops 512 GB and 1 TB Flash Chips Using TSV
Expect 20-30% Cheaper NAND in Late 2018


Original Submission

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  • (Score: 3, Insightful) by bob_super on Wednesday July 19 2017, @04:47PM (6 children)

    by bob_super (1357) on Wednesday July 19 2017, @04:47PM (#541501)

    So, there's that great thing I've been doing for two years, ok? It's great, you're gonna see. And by you're gonna see, I mean, next year. You're totally gonna see next year what I told you I have been doing for a couple years. It's gonna be huge. It will be ready on day 1. Next year.

    • (Score: 4, Insightful) by takyon on Wednesday July 19 2017, @05:20PM (3 children)

      by takyon (881) Subscriber Badge <{takyon} {at} {soylentnews.org}> on Wednesday July 19 2017, @05:20PM (#541521) Journal

      Don't be dense. It is a product that is shipping to customers:

      Shipments of prototypes for development purposes started in June, and product samples are scheduled for release in the second half of 2017. The prototype of this groundbreaking device will be showcased at the 2017 Flash Memory Summit in Santa Clara, California, United States, from August 7-10.

      Actually, do be dense. Be a dense storage unit for mankind.

      --
      [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
      • (Score: 0) by Anonymous Coward on Wednesday July 19 2017, @05:42PM (2 children)

        by Anonymous Coward on Wednesday July 19 2017, @05:42PM (#541536)

        It is a prototype that is shipping to developers.

        • (Score: 2) by takyon on Wednesday July 19 2017, @05:48PM (1 child)

          by takyon (881) Subscriber Badge <{takyon} {at} {soylentnews.org}> on Wednesday July 19 2017, @05:48PM (#541541) Journal

          The developers are customers, and the prototype is a product of Toshiba's production fab. :^)

          --
          [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
          • (Score: 0) by Anonymous Coward on Wednesday July 19 2017, @10:38PM

            by Anonymous Coward on Wednesday July 19 2017, @10:38PM (#541666)

            If it is at that point look for it in 6-8 months.

    • (Score: 1, Offtopic) by DeathMonkey on Wednesday July 19 2017, @05:56PM (1 child)

      by DeathMonkey (1380) on Wednesday July 19 2017, @05:56PM (#541550) Journal

      A lot of people think Aristarchus is actually our local Donald Trump. I hereby nominate bob_super as a possible candidate!

      • (Score: 4, Funny) by aristarchus on Thursday July 20 2017, @05:42AM

        by aristarchus (2645) Subscriber Badge on Thursday July 20 2017, @05:42AM (#541820) Journal

        "Wow, Toshiba is really stacked!" You know, when you are famous and like the President and all, they just let you grab them by the NAND, with or without the TSVs! Because, well, aristarchus should never be confused with an ignorant real estate developer like the Donald Trump. My name will live on for centuries, but the Donald will be forgotten, totally, in a decade. As will Toshiba's innovation in this case. Try to keep a perspective, Soylentils! This is an advance, but only an incremental advance. Kind of like upgrading from Marla to Melania, if you know what I mean. More stacked!

        --
        #freearistarchus!!!
  • (Score: 2) by richtopia on Wednesday July 19 2017, @06:16PM (1 child)

    by richtopia (3160) Subscriber Badge on Wednesday July 19 2017, @06:16PM (#541560) Homepage Journal

    This product looks quite awesome. However Toshiba is shedding their memory group. If all goes well it should be fine, but I could see things get delayed during the difficulties of being purchased.

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