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posted by martyb on Wednesday July 26 2017, @12:12PM   Printer-friendly
from the a-bit-better dept.

Both Toshiba (or whomever ends up buying Toshiba's memory fabrication assets) and Western Digital (WD) have both recently announced plans to produce 3D QLC (four bits per cell) NAND:

Western Digital's SanDisk subsidiary and Toshiba have a long history of jointly developing and manufacturing NAND flash memory. While that relationship has been strained by Toshiba's recent financial troubles and attempts to sell of their share of the memory business, the companies are continuing to develop new flash memory technology and are still taking turns making new announcements. In recent months both companies have started sampling SSDs using their 64-layer BiCS3 TLC 3D NAND and have announced that their next generation BiCS4 3D NAND will be a 96-layer design.

Yesterday Western Digital made a small announcement about their other main strategy for increasing density: storing more bits per memory cell. Western Digital will introduce four bit per cell QLC parts built on their 64-layer BiCS3 process, with a capacity of 768Gb (96GB) per die. This is a substantial increase over the 512Gb BiCS3 TLC parts that will be hitting the market soon, and represents not only an increase in in bits stored per memory cell but an increase in the overall size of the memory array. These new 3D QLC NAND parts are clearly intended to offer the best price per GB that Western Digital can manage, but Western Digital claims performance will still be close to that of their 3D TLC NAND. Western Digital's announcement did not mention write endurance, but Toshiba's earlier announcement of 3D QLC NAND claimed endurance of 1000 program/erase cycles, far higher than industry expectations of 100-150 P/E cycles for 3D QLC and comparable to 3D TLC NAND.

Western Digital will showcase SSDs and removable flash media using QLC NAND at the Flash Memory Summit from August 8-10.

Will QLC NAND endurance become a bigger issue than it is with TLC? Will this be used primarily for high density cold storage like Facebook has asked for?

Previously: Toshiba Teasing QLC 3D NAND and TSV for More Layers
SK Hynix Developing 96 and 128-Layer TLC 3D NAND
Western Digital Announces 96-Layer 3D NAND, Including Both TLC and QLC
Toshiba's 3D QLC NAND Could Reach 1000 P/E Cycles
Toshiba Develops 512 GB and 1 TB Flash Chips Using TSV


Original Submission

Related Stories

Toshiba Teasing QLC 3D NAND and TSV for More Layers

The wide adoption of 3D/vertical NAND with increased feature sizes and endurance will apparently lead to the introduction of low-cost QLC (4 bits per cell) NAND. 3D NAND's increased flash cell size and overprovisioning will counteract the reduction in endurance caused by moving from 3 to 4 bits per cell:

We covered the TSV [Through Silicon Vias] notion here and now take a look at quadruple level cell (QLC) flash technology. Toshiba will present on this and TSVs in a keynote session at the August 6-9 Flash Memory Summit in Santa Clara. The session abstract notes: "New technologies such as QLC (Quadruple Level Cell) BiCS FLASH offer high density, low-cost solutions, while TSV (Through Silicon Via) NAND offers high performance with significant power reduction."

To recap, BiCS stands for Bit Cost Scalable and is Toshiba and flash foundry partner WDC's approach to 3D NAND, the layering of ordinary or planer (2D) NAND chips atop each other. We have 48-layer cells in production and 64-layer ones coming with 96-layer and even 128-layer chips in prospect. Progress beyond 64-layers has problems due to the difficulties in etching holes through the layers and so the TSV idea is to have two layers of layering: two 64-layer chips one on top of the other, with holes through them both, TSVs, for wiring to hold them together and carry out cell activity functions as well.

[...] Back in March, Jeff Ohshima, a Toshiba executive, presented on TSVs and QLC flash at the Non-Volatile Memory Workshop and suggested 88TB QLC 3D NAND SSDs with a 500 write cycle life could be put into production. The Flash Memory Summit keynote could add more colour to this.

Related:

Toshiba and SanDisk Announce 48-Layer 256 Gb 3D NAND
Toshiba Brings Through-Silicon Vias to NAND Flash
Western Digital, SanDisk, and the NAND Market
"String-Stacking" Being Developed to Enable 3D NAND With More Than 100 Layers (NAND devices with 64 layers and above will be difficult to create, so stacking 48-layer devices will be used to increase density)


Original Submission

SK Hynix Developing 96 and 128-Layer TLC 3D NAND 3 comments

SK Hynix is currently developing 96-layer and 128-layer 3D NAND with 3 bits per cell, but may be skipping quad-level cell 3D NAND for some time:

The 64-layer 3D NAND about to land from Micron and Toshiba certainly sounds impressive, but it pales in comparison to what Sk Hynix is working on for future release. The company is developing 96-layer and 128-layer 3D NAND flash. The new flash won't be available for a few years, but that makes it no less exciting. We have yet to see 72-layer 3D from Sk Hynix in our lab, but it will begin shipping soon in the PC401 using 256Gbit TLC die, according to the UNH-IOL list of tested products.

The information we found about the successor to 256Gbit 72-layer 3D TLC shows 96 layers with 512Gbit die capacity. The follow up to that is a massive 1Tbit die from 128-layer TLC from the other South Korean SSD manufacturer with full vertical integration.

Toshiba (or whichever company acquires Toshiba's memory division) may be more likely to introduce QLC 3D NAND.

Previously:
SK Hynix Plans 72-Layer 512 Gb NAND for Late 2017
64-Layer 3D NAND at Computex


Original Submission

Western Digital Announces 96-Layer 3D NAND, Including Both TLC and QLC 2 comments

Western Digital has announced that it will begin production of 96-layer 3D NAND in 2018. It will make triple-level cell and quad-level cell NAND with die capacities ranging from 256 Gb to 1 Tb. QLC NAND is predicted to have 100-150 program/erase cycles (endurance) compared to about 1000 for TLC:

Given such endurance, it is logical to expect 3D QLC NAND to be used for primarily removable storage as well as for ultra-high capacity datacenter drives for the so-called near-WORM (write once read many) storage applications. For example, Toshiba last year discussed a QLC-based datacenter SSD with 100 TB capacity for WORM apps.

Western Digital plans to begin sampling of select 96-layer BiCS4 3D NAND configurations in the second half of this year, but the manufacturer does not specify which dies will sample when. As for mass production, Western Digital intends to start volume manufacturing of their 96-layer 256 Gb 3D NAND in 2018, with other dies to follow later. Based on Western Digital's announcements made earlier, the company will gradually introduce more sophisticated BiCS4 96-layer configurations in 2018 and 2019, before moving to BiCS5 sometimes in 2020. That said, it makes sense to expect the highest capacity BiCS4 ICs to ship later rather than sooner.

[BiCS = "Bit-Cost Scaling". Yes, it does not make sense to me, either. --Ed.]


Original Submission

Toshiba's 3D QLC NAND Could Reach 1000 P/E Cycles 10 comments

While QLC NAND is predicted to have as low as 100 program/erase cycles (endurance), Toshiba has "targeted" 1000 cycles for its upcoming 3D QLC NAND products:

Toshiba last week announced its first 3D NAND flash memory chips featuring [the] QLC (quadruple level cell) BiCS architecture. The new components feature 64 layers and developers of SSDs and SSD [controllers] have already received samples of the devices, which Toshiba plans to use for various types of storage solutions.

[...] Besides [its] intention to produce 768 Gb 3D QLC NAND flash for the aforementioned devices, the most interesting part of Toshiba's announcement is [the] endurance specification for the upcoming components. According to the company, its 3D QLC NAND is targeted for ~1000 program/erase cycles, which is close to TLC NAND flash. This is considerably higher than the amount of P/E cycles (100 – 150) expected for QLC by the industry over the years. At first thought, it comes across [as] a typo - didn't they mean 100?. But the email we received was quite clear:

- What's the number of P/E cycles supported by Toshiba's QLC NAND?
- QLC P/E is targeted for 1K cycles.

Endurance miracle putting QLC on par with TLC, or idle talk about a product that won't be out for 1-2 years?

[Ed. note: If you're wondering what QLC NAND is, here's a quick primer.]

Additional Coverage: The guru of 3D


Original Submission

Toshiba Develops 512 GB and 1 TB Flash Chips Using TSV 9 comments

While other manufacturers are making 512 Gb to 1 Tb 3D NAND flash dies, Toshiba is using through-silicon vias (TSVs) to stack their dies, effectively cramming 384 to 768 layers of 3D NAND into a single chip. Toshiba announced that it was developing this capability back in 2015, and now the first products to use it will be available in 2018:

Toshiba on Wednesday introduced its first BiCS 3D TLC NAND flash chips with 512 GB and 1 TB capacities. . The new ICs stack 8 or 16 3D NAND devices using through silicon vias (TSVs) and are currently among the highest capacity non-volatile memory stacks available in the industry. Commercial products powered by the 512 GB and 1 TB packages are expected to hit the market in 2018, with an initial market focus on high-end enterprise SSDs

Stacking NAND devices to build high capacity flash memory ICs has been used for years to maximize the capacities and performance of SSDs and other solid state storage devices. In many cases, NAND makers use wire-bonding technique to stack multiple memory devices, but it makes packages larger and requires a lot of power for reliable operation. However in more recent years, Toshiba has adopted TSV techniques previously used for ASIC and DRAM devices to stack its NAND ICs, which has enabled it to shrink size of its NAND packages and reduce their power consumption.

TSVs are essentially electrodes that penetrate the entire thickness of a silicon die and connect the dies above and below it in the stack. A bus formed by TSVs can operate at a high data transfer rate, consume less power, and take up less space than a bus made using physical wires. Since 3D NAND is based on vertically stacked memory layers and has numerous vertical interconnects, so far Toshiba has not used TSVs to interconnect such devices. To wed TSV and 3D NAND, Toshiba had to develop a special 512 Gb BiCS NAND die featuring appropriate electrical conductors.

The devices both measure 14 mm × 18 mm. The 8-stack chip has a height of 1.35 mm, and the 16-stack chip has a height of 1.85 mm.

Toshiba press release.

Western Digital Samples 96-Layer 3D QLC NAND with 1.33 Tb Per Die 4 comments

Western Digital Begins to Sample QLC BiCS4: 1.33 Tbit 96-Layer 3D NAND

Western Digital has started sampling its 96-layer 3D NAND chips featuring QLC architecture that stores four bits per cell. The chip happens to be the world's highest-capacity 3D NAND device. The company expects to commence volume shipments of this memory chip already this calendar year.

Western Digital's 96-layer BICS4 3D QLC NAND chip can store up to 1.33 Tb of raw data, or around 166 GB. The IC will be initially used for consumer products Western Digital sells under the SanDisk brand, so think of memory cards (e.g., high-capacity SD and microSD products), USB drives, and some other devices. The manufacturer expects its 3D QLD[sic] NAND memory to be used in a variety of applications, including retail, mobile, embedded, client, and enterprise, but does not elaborate on timing at this point.

The 1.33-Tb BICS4 IC is Western Digital's second-gen 3D QLC NAND device. Last year the company announced its BICS3 64-layer 3D QLC chips featuring a 768 Gb capacity, but it is unclear whether they have ever been used for commercial products. Meanwhile, it is clear that the device was used to learn about 3D QLC behavior in general (i.e., endurance, read errors, retention, etc.)

[...] What is noteworthy is that officially the BiCS4 range was to include both TLC and QLC ICs with capacities ranging from 256 Gb to 1 Tb, so the 1.33 Tb IC is a surprising addition to the lineup which signals Western Digital's confidence of its technology.

Recent products have been using 512 Gb per die NAND, with 768 Gb and 1 Tb on the horizon. Samsung's announced 128 TB SSD was supposed to use 1 Tb 3D QLC dies, so ~1.33 Tb dies could bring that capacity to about 170 TB. Given a couple more generations of NAND or some fancy die/package stacking, and we will probably see a 1 petabyte SSD.

Expect 20-30% Cheaper NAND in Late 2018 7 comments

The 512 Gb dies are coming:

64-layer 3D NAND is shipping, but the 256Gbit die will come and go rapidly. That's what makes this NAND cycle different. Many of the companies we've spoken to do not want to invest in products with such a limited shelf life. The 512Gbit die are right around the corner from the fabs. Some estimates put a major ramp up coming before mid year. The technology offers a 2x capacity increase while taking only a little more space on the wafer. The bits per wafer doesn't double, but it gets very close. The retail products coming in the second half of 2018 with have a heavy impact on SSD pricing. Some estimates from engineers we've spoken with put retail pricing on track for a 20% to 30% reduction over similar-capacity products shipping today.

Emerging technologies and form factors that reduce the material costs will also play a role. Toshiba Memory America showcased the new RC100 NVMe SSD that uses multi-chip packaging to cram the controller and flash in a single package.

Toshiba has described stacking 8-16 512 Gb dies with through silicon vias (TSVs) to create 512 GB and 1 TB packages. Samsung plans to stack 32 256 Gb dies to make 1 TB packages for an upcoming 128 TB SSD.

Previously: SK Hynix Plans 72-Layer 512 Gb NAND for Late 2017
SK Hynix Developing 96 and 128-Layer TLC 3D NAND
Intel First to Market With 64-Layer 3D NAND SSDs
Western Digital Announces 96-Layer 3D NAND, Including Both TLC and QLC
Toshiba's 3D QLC NAND Could Reach 1000 P/E Cycles
WD Announces 64-Layer 3D QLC NAND With 768 Gb Per Die, to be Shown at Flash Memory Summit


Original Submission

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