http://www.tomshardware.com/news/pcie-4.0-5.0-pci-sig-specfication,35325.html
PCIe is the ubiquitous engine that pulls a big part of the computing locomotive down the track—it touches nearly every device in your computer. As such, it is the linchpin for the development of many other technologies, such as storage, networking, GPUs, chipsets, and many other devices. Considering its importance, it isn't surprising to find the PCI-SIG with 750 members worldwide. Unfortunately, large organizations tend to move slowly, and PCIe 4.0 is undoubtedly late to market. PCIe 3.0 debuted in 2010 within the normal four-year cadence, but PCIe 4.0 isn't projected to land in significant quantities until the end of 2017—a seven-year gap.
PCI-SIG representatives attributed part of the delay to industry stagnation. The PCIe 3.0 interface was sufficient for storage, networking, graphics cards, and other devices, for the first several years after its introduction. Over the last two years, a sudden wellspring of innovation exposed PCIe 3.0's throughput deficiencies. Artificial intelligence craves increased GPU throughput, storage devices are migrating to the PCIe bus with the NVMe protocol, and as a result, networking suddenly has an insatiable appetite for more bandwidth.
The industry needs PCIe 4.0 to land soon, and PCI-SIG assures us it will ratify the new specification by the end of 2017. The sluggish ratification process hasn't hampered adoption entirely, though. Several IP vendors already offer 16GT/s controllers, and many vendors have already implemented PCIe 4.0 PHYs into their next-generation products. These companies are plowing ahead with the 0.9 revision of the specification, whereas the final ratified spec debuts at 1.0. PCI-SIG says it is accelerating the development and feedback processes, along with simplifying early specification revisions, in a bid to reduce time to market for future specifications. PCI-SIG indicates that PCIe 4.0 will be a short-lived specification because the organization has fast-tracked PCIe 5.0 for final release in 2019.
[...] AMD has slated PCIe 4.0 for 2020. We imagine Intel is also chomping at the bit to deploy PCIe 4.0 3D XPoint and NVMe SSDs, but the company remains silent on its timeline.
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The industry has been stuck on PCIe 3.0 for roughly seven years, and even though the first support for PCIe 4.0 on the desktop will land soon in AMD's third-gen Ryzen chips and the first PCIe 4.0 SSDs just cropped up, the industry is already adopting PCIe 5.0. The new standard doubles throughput over PCIe 4.0, yielding a data rate of 32 GT/s.
Today PCI-SIG, the organization that defines PCIe standards, announced that it ratified Version 0.9 of the PCI Express 5.0 specification, signaling that end devices will come to market in the near future. (Companies design end devices as early as revision 0.4 and often launch with 0.9.)
[...] PCIe 4.0 brings 64GBps of throughput, while PCIe 5.0 will double that to 128GBps. Both revisions still use the 128b/130b encoding scheme that debuted with PCIe 3.0. PCI-SIG representatives said they are satisfied with the 20% reduction in overhead facilitated by the 128b/130b encoding, and further encoding refinements to reduce the current 1.5% overhead are subject to a diminishing point of returns.
PCIe 5.0 also brings other features, like electrical changes to improve signal integrity, backward-compatible CEM connectors for add-in cards, and backward compatibility with previous versions of PCIe. The PCI-SIG also designed the new standard to reduce latency and tolerate higher signal loss for long-reach applications.
Previously: PCIe 4.0 to be Available This Year, PCIe 5.0 in 2019
PCI-SIG Finalizes PCIe 5.0 Specification: x16 Slots to Reach 64GB/sec
Following the long gap after the release of PCI Express 3.0 in 2010, the PCI Special Interest Group (PCI-SIG) set about a plan to speed up the development and release of successive PCIe standards. Following this plan, in late 2017 the group released PCIe 4.0, which doubled PCIe 3.0's bandwidth. Now less than two years after PCIe 4.0 – and with the first hardware for that standard just landing now – the group is back again with the release of the PCIe 5.0 specification, which once again doubles the amount of bandwidth available over a PCI Express link.
Built on top of the PCIe 4.0 standard, the PCIe 5.0 standard is a relatively straightforward extension of 4.0. The latest standard doubles the transfer rate once again, which now reaches 32 GigaTransfers/second. Which, for practical purposes, means PCIe slots can now reach anywhere between ~4GB/sec for a x1 slot up to ~64GB/sec for a x16 slot. For comparison's sake, 4GB/sec is as much bandwidth as a PCIe 1.0 x16 slot, so over the last decade and a half, the number of lanes required to deliver that kind of bandwidth has been cut to 1/16th the original amount.
Previously:
PCIe 4.0 to be Available This Year, PCIe 5.0 in 2019
Version 0.9 of the PCI Express 5.0 Specification Ratified
Obligatory xkcd
PCI Express Bandwidth to Be Doubled Again: PCIe 6.0 Announced, Spec to Land in 2021
When the PCI Special Interest Group (PCI-SIG) first announced PCIe 4.0 a few years back, the group made it clear that they were not just going to make up for lost time after PCI 3.0, but that they were going to accelerate their development schedule to beat their old cadence. Since then the group has launched the final versions of the 4.0 and 5.0 specifications, and now with 5.0 only weeks old, the group is announcing today that they are already hard at work on the next version of the PCIe specification, PCIe 6.0. True to PCIe development iteration, the forthcoming standard will once again double the bandwidth of a PCIe slot – a x16 slot will now be able to hit a staggering 128GB/sec – with the group expecting to finalize the standard in 2021.
[...] PCIe 6.0, in turn, is easily the most important/most disruptive update to the PCIe standard since PCIe 3.0 almost a decade ago. To be sure, PCIe 6.0 remains backwards compatible with the 5 versions that have preceded it, and PCIe slots aren't going anywhere. But with PCIe 4.0 & 5.0 already resulting in very tight signal requirements that have resulted in ever shorter trace length limits, simply doubling the transfer rate yet again isn't necessarily the best way to go. Instead, the PCI-SIG is going to upend the signaling technology entirely, moving from the Non-Return-to-Zero (NRZ) tech used since the beginning, and to Pulse-Amplitude Modulation 4 (PAM4).
[...] PCIe 6.0 will be able to reach anywhere between ~8GB/sec for a x1 slot up to ~128GB/sec for a x16 slot (e.g. accelerator/video card). For comparison's sake, 8GB/sec is as much bandwidth as a PCIe 2.0 x16 slot, so over the last decade and a half, the number of lanes required to deliver that kind of bandwidth has been cut to 1/16th the original amount.
Previously: PCIe 4.0 to be Available This Year, PCIe 5.0 in 2019
Version 0.9 of the PCI Express 5.0 Specification Ratified
PCIe 5.0 Specification Finalized (yes, that was 3 weeks ago)
(Score: 1, Informative) by Anonymous Coward on Thursday August 31 2017, @09:17PM (4 children)
It has PCIe 4.0 on release.
The bad part is: You need both processors in order to gain access to all the slots :(
(Score: 2) by takyon on Thursday August 31 2017, @10:04PM (3 children)
Thanks for the reminder.
So is anyone planning on running Tails on Talos II for the ultimate paranoid experience?
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by bob_super on Thursday August 31 2017, @10:14PM (2 children)
The ultimate paranoid experience calls for running it airgapped and headless.
But if you want to be really sure, you need batteries and an alternator (or a DC supply). Though, given that China make a lot of alternators and batteries, you should consider avoiding power altogether.
There, peace of mind and cost savings...
(Score: 2) by takyon on Thursday August 31 2017, @10:28PM (1 child)
If you want to talk airgapped you might as well not run a computer at all since you could get Stuxnetted by a trained squirrel with a microSD card.
*Ultimate paranoid experience while still connected to the
spyInter-net.[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by bob_super on Thursday August 31 2017, @10:58PM
If you want to connect to the web safely, run an embedded OS on a Microblaze (Xilinx FPGA soft-core processor).
Running Linux is also possible, but might open up some script attacks.
(Score: 2) by bob_super on Thursday August 31 2017, @09:28PM (2 children)
16GT/s is nice, but 25Gb/s transceivers are becoming a lot more available these days, with good enough EQs that even basic consumers should achieve that speed on high quality extension cards. For something not released yet, stopping at 16 is a bit of a miss...
I'm pretty sure having a straight shot from the processor into 25G/100G/400G optics would make a lot of servers happy.
(Score: 4, Insightful) by forkazoo on Friday September 01 2017, @01:12AM (1 child)
If they tried to roll out 32 GT per lane today, it'd be impractical and terribly expensive. That's why they are targeting that speed for the 2020 spec. They aren't stopping at 16, they are just rolling it out as a huge advance on the current state of the art and then going from there once that's out. It's not particularly unreasonable for a 25 Gb NIC to use 2 PCIe lanes in the mean time.
Faster is better, all other things being equal, but there are a lot of hard problems, and nothing comes for free. (And hell, I am still waiting for 10 Gb to become ubiquitous, let alone 25!)
(Score: 2) by bob_super on Friday September 01 2017, @01:57AM
With 25G becoming more commonplace in data centers, it does matter a lot that you need 2 PCIe lanes. Because 100G connection is 8 lanes, and a 400G connection is a whopping 64 lanes.
40G is still 3 lanes, when it would be 2 at 25G.
Those have a cost, especially when Intel plays PCIe availability games.
Proper 25GT/s PCB design has a cost, too. But not as high as the processor PCIe tax.
(Score: 1) by Booga1 on Thursday August 31 2017, @11:02PM
Considering how long it's been since 4.0 has been promised, I'll not hold my breath any longer for it. So many broken expectations and timelines have worn me out. Ryzen SHOULD have been designed with PCI-e 4.0, but even AMD gave up on waiting. Looks like PCI-e 3.0 will be around for several more years.
(Score: 0) by Anonymous Coward on Thursday August 31 2017, @11:57PM (2 children)
Why would you buy overpriced pre-spec PCIe 4 gear when PCIe 5 will come out the next year?
Is somebody being paid off here?
(Score: 4, Insightful) by forkazoo on Friday September 01 2017, @01:16AM
If you need gear, you buy what exists. Maybe PCIe5 will get delayed. Maybe the spec will be on time, but the hardware will be delayed. Maybe the hardware will be on time, but but insanely expensive or unreliable. Meanwhile, while you wait for PCIe5, everybody is doing stuff with their PCIe4 gear.
Likewise, don't buy software based on a roadmap. Just like hardware, it doesn't matter what amazing things have been promised, because nobody can be sure how the future will play out. If something has enough value, buy it. If something doesn't have enough value, don't buy it. We've been dealing with "Should I wait" questions since people started figuring out better ways to bang rocks together.
(Score: 2) by RamiK on Friday September 01 2017, @07:25AM
These advances in memory bandwidth aren't meaningfully beneficial to the general consumers since loading textures is not a bottleneck in games and CAD. They're there for compute and big data who retire hardware every 1-3years.
compiling...