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posted by Fnord666 on Sunday September 10 2017, @08:49PM   Printer-friendly
from the open-source-SoC-FTW dept.

Submitted via IRC for TheMightyBuzzard

SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that UltraSoC will provide debug and trace technology for the SiFive Freedom platform, based on the RISC-V open source processor specification as part of the DesignShare initiative. UltraSoC's embedded analytics IP will be available through the recently announced SiFive DesignShare ecosystem that gives any company, inventor or maker the ability to harness the power of custom silicon. UltraSoC's debug and trace functionality will enable users of the Freedom platform to access a wide variety of tools and interfaces to use in their developments.

The DesignShare concept enables an entirely new range of applications. Companies like SiFive, UltraSoC and other ecosystem partners have developed efficient, pre-integrated solutions to lower the upfront engineering costs required to bring a custom chip design based on the SiFive Freedom platform to realization. The partnership between SiFive, originator of the industry's first open-source chip platform, and UltraSoC, the industry leader in vendor-neutral on-chip debug and analytics tools, significantly strengthens the ecosystem surrounding RISC-V, the open source processor specification which is often dubbed "the Linux of the semiconductor industry."

[...] Rick O'Connor, executive director of the RISC-V Foundation, commented: "The idea behind the open source movement is that one doesn't have to design everything from scratch. The idea behind DesignShare is to help speed the development of new silicon designs by reducing the barriers of cost, process and integration that have traditionally held back innovation in the semiconductor industry. SiFive, UltraSoC and the other companies that are making their IP available through DesignShare are fundamentally enabling this revolution in an otherwise stagnant industry."

Source: http://markets.businessinsider.com/news/stocks/SiFive-and-UltraSoC-partner-to-accelerate-RISC-V-development-through-DesignShare-1002349996


Original Submission

Related Stories

lowRISC is Hiring: Help Make Open-Source Hardware a Reality. 14 comments

From the lowRISC blog:

We are looking for a talented hardware engineer to join the lowRISC team and help make our vision for an open source, secure, and flexible SoC a reality. Apply now!

lowRISC C.I.C. is a not-for-profit company that aims to demonstrate, promote and support the use of open-source hardware. The lowRISC project was established in 2014 with the aim of bringing the benefits of open-source to the hardware world. It is working to do this by producing a high quality, secure, open, and flexible System-on-Chip (SoC) platform. lowRISC C.I.C. also provides hardware and software services to support the growing RISC-V ecosystem. Our expertise includes the LLVM Compiler, hardware security extensions and RISC-V tools, hardware and processor design.

[...] lowRISC is an ambitious project with a small core team, so you will be heavily involved in the project's development direction. This role will involve frequent work with external contributors and collaborators. While much of the work will be at the hardware level the post will offer experience of the full hardware/software stack, higher-level simulation tools and architectural design issues.

Some practical experience of hardware design with a HDL such as Verilog/SystemVerilog is essential, as is a good knowledge of the HW/SW stack. Ideally, candidates will also have experience or demonstrated interest in some of: SoC design, large-scale open source development, hardware or software security, technical documentation, board support package development and driver development. Industrial experience and higher degree levels are valued, but we would be happy to consider an enthusiastic recent graduate with a strong academic record.

Informal enquires should be made to Alex Bradbury asb@lowrisc.org.

takyon (thanks to an AC): lowRISC is a project to create a "fully open-sourced, Linux-capable, system-on-a-chip"; it is based around RISC-V, the "Free and Open RISC Instruction Set Architecture", which is meant to provide an extensible platform that scales from low-level microcontrollers up to highly parallel, high-bandwidth general-purpose supercomputers.

Reduced instruction set computer (RISC).

Previously: RISC-V Projects to Collaborate
LowRISC Announces its 0.4 Milestone Release
SiFive and UltraSoC Partner to Accelerate RISC-V Development Through DesignShare


Original Submission

Qualcomm Invests in RISC-V Startup SiFive 4 comments

Qualcomm Invests in RISC-V Startup SiFive

Investors are zeroing in on the open standard RISC-V instruction set architecture and the processor intellectual property being developed by a batch of high-flying chip startups.

Last fall, Esperanto Technologies announced a $58 million funding round. The chip IP vendor is incorporating more than 1,000 RISC-V cores onto a single 7-nm chip. Data storage specialist Western Digital is an early investor in Esperanto, Mountain View, Calif.

This week, another RISC-V startup, SiFive, announced a $65.4 million funding round that included new investor Qualcomm Ventures. SiFive, San Mateo, Calif., has so far raised more than $125 million, and is seen as a challenger to chip IP leader Arm.

Observers note that wireless modem leader Qualcomm is among Arm's biggest customers, making its investment in SiFive intriguing. Also participating in the Series D round were existing investors Chengwei Capital of Shanghai along with Sutter Hill Ventures and Spark Capital. Intel Capital and Western Digital also were early investors.

Also at EE Times.

See also: SiFive Acquires USB 2.0 and 3.x IP Portfolio to Strengthen RISC-V SoCs

Previously: RISC-V Projects to Collaborate
SiFive and UltraSoC Partner to Accelerate RISC-V Development Through DesignShare
SiFive Introduces RISC-V Linux-Capable Multicore Processor
SiFive HiFive Unleashed Not as Open as Previously Thought
Linux Foundation and RISC-V Proponents Launch CHIPS Alliance

Separately, a handful of RISC-V proponents launched the CHIPS Alliance, a project of the Linux Foundation to develop a broad set of open-source IP blocks and tools for the instruction set architecture. Initial members include Esperanto, Google, SiFive, and Western Digital. CHIPS stands for Common Hardware for Interfaces, Processors, and Systems.

Esperanto Technologies and SiFive look like the names to watch.

Related: First Open Source RISC-V Implementations Become Available
Western Digital Unveils RISC-V Controller Design
Raspberry Pi Foundation Announces RISC-V Foundation Membership
Western Digital Publishes RISC-V "SweRV" Core Design Under Apache 2.0 License


Original Submission

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  • (Score: 4, Interesting) by Snotnose on Sunday September 10 2017, @10:32PM (9 children)

    by Snotnose (1623) on Sunday September 10 2017, @10:32PM (#566049)

    CSB.
    Several years ago I worked for a well known SOC vendor. We did a respin, typical, chips got 2-4 spins before being released to work out the bugs. We had a board that would randomly reboot up after 1 hour to 1 week. Nobody could figure it out, nor how to re-create it. Even had a "magic" laptop that "caused" the problem to happen more often.

    At the time I was a roving problem solver, so I got the system. Quickly figured out it had reboot because the watchdog timer had fired (quickly because they called me in when it happened and they hadn't powered down the system, it it was a JTAG register read. Took it all to my desk, fired it up, and waited. (Relatively) quickly it rebooted, I stepped through the init code, which was an array of functions to call (init_this, init_that, init_me, init_you). 6th entry turned on the memory manager, after which all memory was in great shape. Figured out which process it was in when it crashed, and restarted it. While it ran I went over the code, especially any changes made to that process. Which was easy, because it hadn't changed in a couple years.

    To keep a long story long, it rebooted again. Same process. So, I made a 255 byte in memory array with a pointer to the next entry. In the code I put a checkpoint at all decision points. That is, for code "if foo do this else that", I'd put checkpoint 10 at this and 20 at that. Every time a reboot happened I'd look at my checkpoint array to see where it was last, and add more checkpoints. Hell, I added checkpoints all over that code. Took 20 minutes to code and compile, days to get results. (Relatively) Didn't take long to narrow it down to a register read. It was a chip status register, and about 1 time in a million when it was read the chip hung. Commented out the read, and things were groovy.

    Total time for tracking down the problem? Maybe 8 hours. Real time for tracking down the problem? About 3 weeks. Remember, it would run for on average 2-3 days before rebooting.

    Worst part of the whole thing? We were short of JTAG boxes, and there wasn't one to spare for me to use for my regular work. I spent 3 weeks twiddling my thumbs waiting for a reboot, nothing to do but read code that had worked for years and hadn't changed, and surfing a young internet (I don't think /. nor fark existed at the time, or I hadn't found them yet).

    --
    Why shouldn't we judge a book by it's cover? It's got the author, title, and a summary of what the book's about.
    • (Score: 3, Interesting) by RamiK on Sunday September 10 2017, @11:18PM

      by RamiK (1813) on Sunday September 10 2017, @11:18PM (#566058)

      God bless git-bisect and OpenOCD.

      --
      compiling...
    • (Score: 2) by LoRdTAW on Monday September 11 2017, @12:22AM (7 children)

      by LoRdTAW (3755) on Monday September 11 2017, @12:22AM (#566070) Journal

      Several years ago I worked for a well known SOC vendor.
      ...
      and surfing a young internet (I don't think /. nor fark existed at the time, or I hadn't found them yet).

      Several? More like tens.

      • (Score: 4, Informative) by Gaaark on Monday September 11 2017, @01:19AM (4 children)

        by Gaaark (41) on Monday September 11 2017, @01:19AM (#566075) Journal

        When you get old, everything becomes just a while ago until you stop and think about it.

        I still have to think about how old I am: my brain thinks I am only 36: my body reminds me I am over 50.

        Getting old sucks... If I remember correctly, lol.

        --
        --- Please remind me if I haven't been civil to you: I'm channeling MDC. ---Gaaark 2.0 ---
        • (Score: 2) by LoRdTAW on Monday September 11 2017, @01:53AM (3 children)

          by LoRdTAW (3755) on Monday September 11 2017, @01:53AM (#566088) Journal

          When you get old, everything becomes just a while ago until you stop and think about it.

          (off topic, but, fuck it) Amen. I am in my late 30's and realizing that since about 30, everything feels like it was just two or three years ago when it was closer to ten years. It's scary how time just seems to disappear in "gaps". I was just at my friends daughters second birthday party and we were talking about a trip we all made and realized it was 15 years ago. We all agreed that it only felt like a few years ago so it must be universal.

          My theory? As we age we slow down physically and fall into a routine that blends one week into the next. 10 Wake, shower, eat, commute, work, eat, work, commute, putter, eat, putter, sleep, GOTO 10. This goes on to the point where you can't tell one week from another. "Did I do that thing last week or last month?" becomes the norm. I believe the antidote is taking up a physical activity to keep moving and taking more trips. You have to break up that bland routine. This gif sums it up perfectly: https://giphy.com/gifs/never-cycle-ending-9hPjzuqQh8Bna [giphy.com]

          • (Score: 3, Insightful) by Anonymous Coward on Monday September 11 2017, @02:08AM

            by Anonymous Coward on Monday September 11 2017, @02:08AM (#566093)

            > fall into a routine that blends one week into the next.

            When you get older (I'm early 60s) it starts to seem more like internal clocks work on ratios:
              + from age 5 to 6 you age one year, or you are 20% older
              + from age 50 to 60 you age 10 years, also 20% older.
            The two feel about the same subjectively (to me). New experiences are added a lot faster when young, we get jaded and don't do so many new things as we age. 20% more age adds about 20% more experiences.

          • (Score: 2) by crafoo on Monday September 11 2017, @01:23PM (1 child)

            by crafoo (6639) on Monday September 11 2017, @01:23PM (#566217)

            Sounds like you are comfortable. Enjoy it I guess. You don't necessarily have to live like this.

            • (Score: 2) by LoRdTAW on Monday September 11 2017, @01:47PM

              by LoRdTAW (3755) on Monday September 11 2017, @01:47PM (#566219) Journal

              Yea, I've been in a rut lately. Changing little by little though.

      • (Score: 2) by Snotnose on Monday September 11 2017, @01:32AM (1 child)

        by Snotnose (1623) on Monday September 11 2017, @01:32AM (#566079)

        Several? More like tens.

        I'm thinking 2004-2005. Based on looking at my resume more than anything else. I do know a couple years later my boss's house burned down in a big wildfire (2007).

        --
        Why shouldn't we judge a book by it's cover? It's got the author, title, and a summary of what the book's about.
        • (Score: 2) by LoRdTAW on Monday September 11 2017, @02:09AM

          by LoRdTAW (3755) on Monday September 11 2017, @02:09AM (#566095) Journal

          Slashdot started 19 years ago! I was thinking mid/late 90's.

  • (Score: 1, Funny) by Anonymous Coward on Monday September 11 2017, @06:19PM

    by Anonymous Coward on Monday September 11 2017, @06:19PM (#566301)

    keep it up people! maybe we'll have a thriving open hardware ecosystem in my lifetime!

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