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posted by martyb on Monday October 02 2017, @08:08PM   Printer-friendly
from the how-many-atoms-wide-is-that? dept.

GlobalFoundries: Next-generation chip factories will cost at least $10 billion

The economics of the chip industry are pretty staggering. Sanjay Jha, CEO of contract chip manufacturer Globalfoundries, recently told me that it could cost between $10 billion and $12 billion to build a next-generation chip factory based on the latest technology, dubbed 7-nanometer production. And one for the generation after that, dubbed 5-nanometer production, could cost $14 billion to $18 billion.

There are only a few companies in the world that can afford to spend that much money on a chip factory. And they can do it because those chips are expected to generate billions of dollars in revenue over the life of the factory.

Dean Takahashi from VentureBeat interviewed Sanjay Jha, CEO of GlobalFoundries:

Basically, the numbers don't mean much these days. I think Samsung has talked about 10nm, 11nm, 14nm, 8nm, 7nm, 6nm. I don't know what they mean. The way to think about 12nm is it has higher performance and more scale than 14nm. It's not quite the scaling or performance of 10nm. Performance may be very close to 10nm, though.

What has happened, as the line widths get closer, it's getting harder and harder to get incremental performance. You can get scale that you want, but getting performance is harder. You can get some power consumption reduction, as well. With 14nm, most people use .8. At 10nm, most people are using .7. As you go, there's a clear scaling with the ratio of the squares of those two numbers. That gives you about 20-25 percent reduction in power consumption. So we deliver performance, some power consumption reduction, and scaling.

[...] VB: Going back to where the specs are on nanometers, how do customers view the problem of figuring out who's really ahead of the game as far as manufacturing?

Jha: They look at four things. They look at density, performance, power consumption, and cost. We call it PPAC. That's what most customers care about. They don't care about 12nm or 10nm. Even if the density of 12nm is a little lower than 10nm, if the complexity of the process is lower and the cost is lower and the power consumption may be lower, that may allow them to go after the mobile space a little better than 10nm. They look at the PPAC and target it to particular models.

Rock's law.

Related: AMD, GlobalFoundries Renew Vows, Focus on Path to 7nm
IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
AMD Expected to Release Ryzen CPUs on a 12nm Process in Q1 2018


Original Submission

Related Stories

AMD, GlobalFoundries Renew Vows, Focus on Path to 7nm 17 comments

AMD and its primary fab partner GlobalFoundries have signed an updated five-year wafer supply agreement that will extend through the end of 2020. The restructuring simultaneously deepens the commitment between the partners and gives AMD limited freedom to see other foundries. In exchange, GlobalFoundries will get some additional compensation.

Per the terms of the agreement, which pertains to AMD's microprocessor, graphics processor, and semi-custom products, AMD will make $25 million cash installments to GlobalFoundries over the next four quarters, for a total cash transfer of $100 million. Beginning in 2017, AMD will be required to make quarterly payments to GlobalFoundries based on the volume of certain wafers it is obtaining from another foundry.

The agreement also stipulates annual wafer purchase targets for the five-year period, sets fixed wafer prices for 2016, and provides a framework for yearly wafer pricing. If annual targets are not met, a penalty will be imposed based on the difference between actual wafer purchases and the target for that year.

takyon: Those are some of the costs of outsourcing your semiconductor fabrication. Let's hope AMD meets those targets.


Original Submission

IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors 10 comments

IBM, which demonstrated the world's first 7nm process silicon chip in 2015, has followed up at the 5nm node. Extreme ultraviolet lithography was required:

IBM, working with Samsung and GlobalFoundries, has unveiled the world's first 5nm silicon chip. Beyond the usual power, performance, and density improvement from moving to smaller transistors, the 5nm IBM chip is notable for being one of the first to use horizontal gate-all-around (GAA) transistors, and the first real use of extreme ultraviolet (EUV) lithography.

GAAFETs are the next evolution of tri-gate finFETs: finFETs, which are currently used for most 22nm-and-below chip designs, will probably run out of steam at around 7nm; GAAFETs may go all the way down to 3nm, especially when combined with EUV. No one really knows what comes after 3nm.

[...] One major advantage of IBM's 5nm GAAFETs is a significant reduction in patterning complexity. Ever since we crossed the 28nm node, chips have become increasingly expensive to manufacture, due to the added complexity of fabricating ever-smaller features at ever-increasing densities. Patterning is the multi-stage process where the layout of the chip—defining where the nanosheets and other components will eventually be built—is etched using a lithographic process. As features get smaller and more complex, more patterning stages are required, which drives up the cost and time of producing each wafer.

[...] IBM says that, compared to commercial 10nm chips (presumably Samsung's 10nm process), the new 5nm tech offers a 40 percent performance boost at the same power, or a 75 percent drop in power consumption at the same performance. Density is also through the roof, with IBM claiming it can squeeze up to 30 billion transistors onto a 50-square-millimetre chip (roughly the size of a fingernail), up from 20 billion transistors on a similarly-sized 7nm chip.

Press release. Also at The Verge, TechCrunch, EE Times, PCMag, and CNET.

Related:
Samsung Plans a "4nm" Process


Original Submission

AMD Expected to Release Ryzen CPUs on a 12nm Process in Q1 2018 10 comments

AMD's high Ryzen sales may have convinced the company to release a new version on a slightly improved process in Spring 2018:

AMD has informed its partners that it plans to launch in February 2018 an upgrade version of its Ryzen series processors built using a 12nm low-power (12LP) process at Globalfoundries, according to sources at motherboard makers.

The company will initially release the CPUs codenamed Pinnacle 7, followed by mid-range Pinnacle 5 and entry-level Pinnacle 3 processors in March 2018, the sources disclosed. AMD is also expected to see its share of the desktop CPU market return to 30% in the first half of 2018.

AMD will launch the low-power version of Pinnacle processors in April 2018 and the enterprise version Pinnacle Pro in May 2018.

The new "Pinnacle Ridge" chips appear to be part of a Zen 1 refresh rather than "Zen 2", which is expected to ship in 2019 on a 7nm process. The 12nm Leading-Performance (12LP) process was described by GlobalFoundries as providing 15% greater circuit density and a 10% performance increase compared to its 14nm FinFET process.

AMD has yet to release 14nm "Raven Ridge" CPUs for laptops.

Also at Wccftech. HPCwire article about the 12LP process.

Previously: AMD Ryzen Launch News
AMD's Ryzen Could be Forcing Intel to Release "Coffee Lake" CPUs Sooner
AMD Ryzen 3 Reviewed


Original Submission

TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020 3 comments

Taiwan Semiconductor Manufacturing Company (TSMC) plans to make so-called "5nm" chips starting in early 2020:

TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC's 5 nm process starting from early 2020. When all three phases of the manufacturing facility are completed, its wafer starts capacity will exceed one million 300-mm wafers per year, comparable with other three GigaFabs operated by TSMC.

TSMC's Fab 18 will be located in Tainan (in the Southern Taiwan Science Park), and will be built in three phases. The construction of the first phase or segment of the building will be completed in about a year from now, after which TSMC will move in equipment sometime in early 2019. In about two years from now, the company expects to start volume production of chips using its 5 nm process technology at the Fab 18/phase 1. Construction of the second and the third phases will commence in Q3 2018 and Q3 2019. The two phases will start volume production in 2020 and 2021, respectively.

Extreme ultraviolet (EUV) lithography could be used to make "7nm" chips, but not "5nm" yet.

Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm


Original Submission

"3nm" Test Chip Taped Out by Imec and Cadence 13 comments

Imec and Cadence Tape Out Industry's First 3nm Test Chip

The world-leading research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. today announced that its extensive, long-standing collaboration has resulted in the industry's first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.

A tape-out is the final step before the design is sent to be fabricated.

Meanwhile, Imec is looking towards nodes smaller than "3nm":

[...] industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, according to the International Technology Roadmap for Semiconductors (ITRS) version 2.0. Another organization, Imec, is more aggressive with the timetable, saying that 2.5nm or thereabouts will arrive by 2024.

Also at EE Times.

Related: TSMC Plans New Fab for 3nm
Samsung Plans a "4nm" Process
IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020


Original Submission

Samsung Preparing to Build Another Memory Fab Near Pyeongtaek for $27.8 Billion 5 comments

Samsung Preps to Build Another Multi-Billion Dollar Memory Fab Near Pyeongtaek

Samsung has begun preparations to build another semiconductor production facility near Pyeongtaek, South Korea. The fab will produce various types of memory as the market demands, and if unofficial information is correct, the new fab may be larger than the adjacent fab that began operations last year.

At present the upcoming fab is called the P2 Project and it will be located adjacent to the existing fab near Pyeongtaek. Samsung has already started to establish infrastructure for the production facility — it ordered the construction of gas pipes for the new production facility in January and is expected to start other works shortly. ETNews reports that Samsung is looking at investing ₩30 trillion ($27.8 billion) in the new P2 Project facility, but does not elaborate whether the number represents total investments, or initial investments. ₩30 trillion is the total amount of money that Samsung has already invested and plans to invest in its existing fab near Pyeongtaek by 2021. Considering the fact that the P2 is in an early stage of planning, it is unlikely that the company has finalized its investments plans.

Related: Samsung Set to Outpace Intel in Semiconductor Revenues
Samsung Could Boost NAND Production Capacity, WD Intervenes in Toshiba Memory Sale
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
Samsung's Second Generation 10nm-Class DRAM in Production
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020


Original Submission

GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack 15 comments

GlobalFoundries has halted development of its "7nm" low power node, will fire 5% of its staff, and will also halt most development of smaller nodes (such as "5nm" and "3nm"):

GlobalFoundries on Monday announced an important strategy shift. The contract maker of semiconductors decided to cease development of bleeding edge manufacturing technologies and stop all work on its 7LP (7 nm) fabrication processes, which will not be used for any client. Instead, the company will focus on specialized process technologies for clients in emerging high-growth markets. These technologies will initially be based on the company's 14LPP/12LP platform and will include RF, embedded memory, and low power features. Because of the strategy shift, GF will cut 5% of its staff as well as renegotiate its WSA and IP-related deals with AMD and IBM. In a bid to understand more what is going on, we sat down with Gary Patton, CTO of GlobalFoundries.

[...] Along with the cancellation of the 7LP, GlobalFoundries essentially canned all pathfinding and research operations for 5 nm and 3 nm nodes. The company will continue to work with the IBM Research Alliance (in Albany, NY) until the end of this year, but GlobalFoundries is not sure it makes sense to invest in R&D for 'bleeding edge' nodes given that it does not plan to use them any time soon. The manufacturer will continue to cooperate with IMEC, which works on a broader set of technologies that will be useful for GF's upcoming specialized fabrication processes, but obviously it will refocus its priorities there as well (more on GF's future process technologies later in this article).

So, the key takeaway here is that while the 7LP platform was a bit behind TSMC's CLN7FF when it comes to HVM – and GlobalFoundries has never been first to market with leading edge bulk manufacturing technologies anyway – there were no issues with the fabrication process itself. Rather there were deeper economic reasons behind the decision.

GlobalFoundries would have needed to use deep ultraviolet (DUV) instead of extreme ultraviolet (EUV) lithography for its initial "7nm" chips. It would have also required billions of dollars of investment to succeed on the "7nm" node, only to make less "7nm" chips than its competitors. The change in plans will require further renegotiation of GlobalFoundries' and AMD's Wafer Supply Agreement (WSA).

Meanwhile, AMD will move most of its business over to TSMC, although it may consider using Samsung:

GlobalFoundries Spins Off ASIC Solutions Division, Creating a New Subsidiary: Avera Semiconductor 5 comments

GlobalFoundries Establishes Avera Semiconductor: a Custom Chip Company

GlobalFoundries this week announced that it has spun off its ASIC Solutions division, establishing Avera Semiconductor, a wholly owned subsidiary that will help fabless chip developers to design their products. Avera will work closely with GlobalFoundries' customers to enable them take advantage of various process technologies that GF has, but the company will also establish ties with other contract makers of semiconductors to help their clients develop chips to be made using leading edge process technologies at 7 nm and beyond.

[...] The new wholly owned subsidiary of GlobalFoundries has over 850 employees, an annual revenue of over $500 million, and ongoing projects worth $3 billion. By working not only with clients of GlobalFoundries, but expanding to customers of companies like Samsung Foundry and TSMC, Avera has a chance to increase its earnings over time. Avera Semi is led by Kevin O'Buckley, a former head of ASIC Solutions, who joined GlobalFoundries from IBM.

Shuffling money on the Titanic?

Previously: AMD, GlobalFoundries Renew Vows, Focus on Path to 7nm
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
AnandTech Interview With the CTO of GlobalFoundries: 7nm EUV and 5 GHz Clock Speeds
GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack

Related: Can Intel Really Share its Fabs?


Original Submission

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  • (Score: 2) by Scrutinizer on Monday October 02 2017, @10:24PM (8 children)

    by Scrutinizer (6534) on Monday October 02 2017, @10:24PM (#576264)

    I'm still waiting for chip technology to make the jump into the third dimension. We have crazy sci-fi semiconductor technology [wikipedia.org] at our fingertips, if perhaps not within our grasp, that may help to facilitate such a change.

    ...

    I have just discovered that the diamond crystal wafers made possible by chemical vapor deposition seem to be downplayed or omitted by the new owner of the patents in favor of OOH SHINY jewelry. Perhaps our new diamond-powered AI overlords will have to wait another ~14 years until the patents expire...

    • (Score: 3, Informative) by mhajicek on Monday October 02 2017, @10:35PM (3 children)

      by mhajicek (51) Subscriber Badge on Monday October 02 2017, @10:35PM (#576272)

      Stacking chips makes thermal dissipation difficult.

      --
      The spacelike surfaces of time foliations can have a cusp at the surface of discontinuity. - P. Hajicek
      • (Score: 0) by Anonymous Coward on Monday October 02 2017, @11:21PM (1 child)

        by Anonymous Coward on Monday October 02 2017, @11:21PM (#576299)

        Quite true. The thermal resiliency of diamond semiconductors (as compared to silicon-based versions) is hoped to allow more leeway in dealing with the heat problem. I think I'd be happy with a monstrosity of a chip layered with built-in heat pipes between each section, particularly after I finish my move to northern Alaska...

      • (Score: 2) by JoeMerchant on Tuesday October 03 2017, @12:33PM

        by JoeMerchant (3937) on Tuesday October 03 2017, @12:33PM (#576552)

        True, though with the consistent reductions in thermal output (per gate), do we really need to keep the traces so close to each other? Sure: use a 5nm process, but space the traces at 20nm (6% density) and then stack them 16 layers deep for a net 1.25nm spacing - the space between could include vertical heat pipes.

        New ideas, new processes, risk. Why take risks when you can invest $20B to net $100B in 5 years time?

        --
        Україна досі не є частиною Росії Слава Україні🌻 https://news.stanford.edu/2023/02/17/will-russia-ukraine-war-end
    • (Score: 2) by takyon on Tuesday October 03 2017, @12:30AM

      by takyon (881) <{takyon} {at} {soylentnews.org}> on Tuesday October 03 2017, @12:30AM (#576326) Journal
    • (Score: 2) by tibman on Tuesday October 03 2017, @12:39AM (1 child)

      by tibman (134) Subscriber Badge on Tuesday October 03 2017, @12:39AM (#576330)

      This is the closest thing i've seen in production: https://en.wikipedia.org/wiki/High_Bandwidth_Memory [wikipedia.org]

      --
      SN won't survive on lurkers alone. Write comments.
      • (Score: 2) by JoeMerchant on Tuesday October 03 2017, @01:47PM

        by JoeMerchant (3937) on Tuesday October 03 2017, @01:47PM (#576577)

        With process density so high, I don't understand why we haven't started seeing high capacity integrated RAM (presumably very high speed) on-die with the processor.

        --
        Україна досі не є частиною Росії Слава Україні🌻 https://news.stanford.edu/2023/02/17/will-russia-ukraine-war-end
    • (Score: 2) by TheRaven on Tuesday October 03 2017, @08:51AM

      by TheRaven (270) on Tuesday October 03 2017, @08:51AM (#576499) Journal
      Here's the problem: Moore's law is still here, but Dennard Scaling isn't. We're still getting double the number of transistors per dollar every couple of years, but we're not getting the reduction in power consumption per transistor. You double the number of transistors, you (almost) double the power consumption. Going 3D doesn't help with this, if anything it makes it worse, because dissipating the heat from the middle is a lot harder.
      --
      sudo mod me up
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