Intel's upcoming 10nm Cannon Lake CPUs will include support for AVX-512 instructions, even in some consumer-oriented SKUs:
A new update to the Intel document for software developers indicates that the company will begin to introduce various AVX-512 instruction set extensions to its consumer CPUs soon. This will start from the codenamed Cannon Lake (CNL) and Ice Lake (ICL) processors, made using 10 nm process technologies. The new extensions will enable future chips to improve performance in certain applications. One of the main questions on AVX-512 is which consumer programs will actually support the AVX-512 when these CNL and ICL processors hit the market. In addition to the AVX-512, the upcoming processors will introduce a host of other new non-AVX-512 instructions.
According to the Intel Architecture Instruction Set Extensions and Future Features Programming Reference document, Intel's Cannon Lake CPUs will support AVX512F, AVX512CD, AVX512DQ, AVX512BW, and AVX512VL. This will bring the feature set of these CPUs to the current level of the Skylake-SP based processors. In addition, the Cannon Lake microarchitecture will support the AVX512_IFMA and AVX512_VBMI commands, but at this point, it is unclear whether the support will be limited to servers, or will also be featured in the consumer processors (the latter scenario is likely based on the document wording, but remains unclear).
Intel originally promised to release Cannon Lake processors in 2016 – 2017 timeframe, but delayed introduction of its 10 nm process technology to 2018, thus postponing the CPU launch as well. Initially it was expected that the Cannon Lake CPUs would generally resemble the Kaby Lake and Coffee Lake chips with some refinements, but the addition of the AVX-512 support means a rather tangible architecture improvement. For AVX-512, large the[sic] chunks of data require massive memory bandwidth, which the Skylake-SP cores get due to large caches and more memory controllers. Keeping in mind memory bandwidth and power consumption factors, the AVX-512 might not be supported by all Cannon Lake client CPUs, but only by those aimed at higher-performance machines (i.e., no AVX-512 for ULP mobile parts as well as entry-level desktop SKUs, but this is [speculation] at this point). Meanwhile, [the] good news is that by the time AVX-512-supporting Cannon Lake processors arrive, programs for client PCs that take advantage of the latest extensions will likely be available.
Previously: AVX-512: A "Hidden Gem"?
Intel's Skylake-SP vs AMD's Epyc
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Upcoming Intel processors will support scalable AVX-512 instructions, which one former Intel employee calls a "hidden gem":
Imagine if we could use vector processing on something other than just floating point problems. Today, GPUs and CPUs work tirelessly to accelerate algorithms based on floating point (FP) numbers. Algorithms can definitely benefit from basing their mathematics on bits and integers (bytes, words) if we could just accelerate them too. FPGAs can do this, but the hardware and software costs remain very high. GPUs aren't designed to operate on non-FP data. Intel AVX introduced some support, and now Intel AVX-512 is bringing a great deal of flexibility to processors. I will share why I'm convinced that the "AVX512VL" capability in particular is a hidden gem that will let AVX-512 be much more useful for compilers and developers alike.
Fortunately for software developers, Intel has done a poor job keeping the "secret" that AVX-512 is coming to Intel's recently announced Xeon Scalable processor line very soon. Amazon Web Services has publically touted AVX-512 on Skylake as coming soon!
It is timely to examine the new AVX-512 capabilities and their ability to impact beyond the more regular HPC needs for floating point only workloads. The hidden gem in all this, which enables shifting to AVX-512 more easily, is the "VL" (vector length) extensions which allow AVX-512 instructions to behave like SSE or AVX/AVX2 instructions when that suits us. This is a clever and powerful addition to enable its adoption in a wider assortment of software more quickly. The VL extensions mean that programmers (and compilers) do not need to shift immediately from 256-bits (AVX/AVX2) to 512-bits to use the new bit/byte/word manipulations. This transitional benefit is useful not only for an interim, but also for applications which find 256-bits more natural (perhaps a small, but important, subset of problems).
Will it be enough to stave off "Epyc"?
AnandTech compared Intel's Skylake-SP chips to AMD's Epyc chips:
We can continue to talk about Intel's excellent mesh topology and AMD strong new Zen architecture, but at the end of the day, the "how" will not matter to infrastructure professionals. Depending on your situation, performance, performance-per-watt, and/or performance-per-dollar are what matters.
The current Intel pricing draws the first line. If performance-per-dollar matters to you, AMD's EPYC pricing is very competitive for a wide range of software applications. With the exception of database software and vectorizable HPC code, AMD's EPYC 7601 ($4200) offers slightly less or slightly better performance than Intel's Xeon 8176 ($8000+). However the real competitor is probably the Xeon 8160, which has 4 (-14%) fewer cores and slightly lower turbo clocks (-100 or -200 MHz). We expect that this CPU will likely offer 15% lower performance, and yet it still costs about $500 more ($4700) than the best EPYC. Of course, everything will depend on the final server system price, but it looks like AMD's new EPYC will put some serious performance-per-dollar pressure on the Intel line.
The Intel chip is indeed able to scale up in 8 sockets systems, but frankly that market is shrinking fast, and dual socket buyers could not care less.
Meanwhile, although we have yet to test it, AMD's single socket offering looks even more attractive. We estimate that a single EPYC 7551P would indeed outperform many of the dual Silver Xeon solutions. Overall the single-socket EPYC gives you about 8 cores more at similar clockspeeds than the 2P Intel, and AMD doesn't require explicit cross socket communication - the server board gets simpler and thus cheaper. For price conscious server buyers, this is an excellent option.
However, if your software is expensive, everything changes. In that case, you care less about the heavy price tags of the Platinum Xeons. For those scenarios, Intel's Skylake-EP Xeons deliver the highest single threaded performance (courtesy of the 3.8 GHz turbo clock), high throughput without much (hardware) tuning, and server managers get the reassurance of Intel's reliable track record. And if you use expensive HPC software, you will probably get the benefits of Intel's beefy AVX 2.0 and/or AVX-512 implementations.
AMD's flagship Epyc CPU has 32 cores, while the largest Skylake-EP Xeon CPU has 28 cores.
Quoted text is from page 23, "Closing Thoughts".
[Ed. note: Article is multiple pages with no single page version in sight.]
Previously: Google Gets its Hands on Skylake-Based Intel Xeons
Intel Announces 4 to 18-Core Skylake-X CPUs
AMD Epyc 7000-Series Launched With Up to 32 Cores
Intel's Skylake and Kaby Lake CPUs Have Nasty Microcode Bug
AVX-512: A "Hidden Gem"?
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(Score: 2) by Snotnose on Friday October 20 2017, @12:50AM (13 children)
I was under the impression what mattered was small scale lithography, for more bang for the wafer, less watts per chip, and faster execution due to shorter paths. Now you're saying something as revolutionary as an enhanced instruction set might play a role?
wat do? Process improvements, or engineering improvements? How shall I bet my 401k tomorrow?
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(Score: 1, Flamebait) by Ethanol-fueled on Friday October 20 2017, @01:07AM (11 children)
As a computer science expert who studied the MIPS processor and once coded a program to calculate primes using MIPS assembly(I believe it was 200 lines or so), I declare that this is Intel going after the lower-end GPUs by having one shit processor suited for multiple tasks. And if there's one semiconductor manufacturer who would Jew anybody, it's Intel.
(Score: 2) by Snotnose on Friday October 20 2017, @01:28AM (3 children)
As someone who back in 2000 or so tried to make the microsoft-compatible test pass on a MIPS (they had a test suite the processor had to pass), and proved they never would be (due to the way the MIPS did it's addressing), I don't remember the point but don't think MIPS was ever a Microsoft approved CPU.
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(Score: 2) by FatPhil on Friday October 20 2017, @01:35PM (2 children)
Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves
(Score: 0) by Anonymous Coward on Friday October 20 2017, @02:50PM (1 child)
M$ ported windoze to MIPS and alpha in the late 90s to check intel's consumer targeting plans (indeo video).
AFAIK by 2000 M$ and intel were besties again and the ports were forgotten.
(Score: 2) by forkazoo on Friday October 20 2017, @07:43PM
There was a 64 bit beta version of Windows 2000 for Alpha that was made, but never released. It apparently more or less worked, to the extent that it could given the lack of Alpha native software to do anything with. I had an Alpha with NT-4 on it at one point that was kind of a novelty. It worked fine, and was still technically fully supported by the year 2000.
Windows mobile supported MIPS long after NT stopped supporting it on the desktop, so Visual Studio retained the ability to compile to odd architectures for a surprisingly long time. A quick Googling mentions MIPS support still being in VS 2008.
(Score: 0) by Anonymous Coward on Friday October 20 2017, @01:35AM
Hold our camel piss. We present Alluha Ackbar, the inbred CPU that uses a burka for a heatsink, has a nine year old co-processor and runs hotter than a jihadi suicide belt. - SAIB Foundries.
(Score: 0) by Anonymous Coward on Friday October 20 2017, @02:34AM (3 children)
No doubt. Isn't AMD owned by a bunch of Arabs now?
(Score: 3, Informative) by takyon on Friday October 20 2017, @03:03AM (2 children)
https://en.wikipedia.org/wiki/GlobalFoundries [wikipedia.org]
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 0) by Anonymous Coward on Friday October 20 2017, @04:00AM
But the Chinese physically control its tangibles.
(Score: 0) by Anonymous Coward on Friday October 20 2017, @08:32PM
Jews pulling the strings at Intel and AMD on its way to being owned by a bunch of Arabs. Finally the religious war of which x86 processor is better can reach its penultimate apocalyptic conclusion.
IMD (Islamic Micro Devices): If your processor doesn't burn hot with the rage of Allah it's not Halal!
(Score: 0) by Anonymous Coward on Friday October 20 2017, @02:59AM
Come on! You're not a "computer science expert". You're just stupid.
(Score: 2) by bob_super on Friday October 20 2017, @05:42PM
> And if there's one semiconductor manufacturer who would Jew anybody, it's Intel.
Considering how their Israel group saved their butt when they were quagmired in Netburst Megahurtz wars, that's quite natural...
(Score: 2, Informative) by Anonymous Coward on Friday October 20 2017, @02:36AM
When new instructions give access to more registers and wider registers, yes, instruction set matters.
ZMM0-ZMM31 provide four times as much register space as YMM0-YMM15.