from the whatever-will-they-do-with-the-one-billion-leftover-apples? dept.
From a Western Digital press release:
Western Digital Corp. (NASDAQ: WDC) announced today at the 7th RISC-V Workshop that the company intends to lead the industry transition toward open, purpose-built compute architectures. In his keynote address, Western Digital's Chief Technology Officer Martin Fink expressed the company's commitment to [...] transitioning its own consumption of processors – over one billion cores per year – to RISC-V.
Related Stories
Western Digital is beginning to use in-house controllers in its new NVMe (Non-Volatile Memory Express) SSDs, but has confirmed that they do not contain RISC-V cores just yet:
Western Digital has announced their first client NVMe SSDs with their SanDisk 64-layer 3D TLC NAND. These drives are also the first to feature Western Digital's new in-house NVMe SSD controllers. This is a major shift in strategy away from third-party controllers (mostly Marvell) toward complete vertical integration.
The new SSDs are called the Western Digital SN720 and Western Digital SN520. Branding for these is a bit of a mess with the drives bearing the Western Digital name and model numbers that almost fit in with the HGST Ultrastar SN200 and SN260 enterprise NVMe SSDs, but the product information is on the SanDisk website and the target market is similar to that of SanDisk's business/OEM drives like the X400 and X600 SATA SSDs. Western Digital may be trying to unify and simplify their several brands, but it's a work in progress.
[...] Western Digital hasn't disclosed what kind of processor cores are used in their NVMe controllers, but they did confirm that these aren't using the RISC-V architecture—those products won't be arriving until next year at the earliest. The Western Digital NVMe controllers are probably using ARM Cortex-R cores like most SSD controllers.
Early to embed and early to rise? Western Digital drops veil on SweRVy RISC-V based designs
Western Digital today finally flashed the results of its vow to move a billion controller cores to RISC-V designs. WD said last year it needed an open and extensible CPU architecture for its purpose-built drive controllers and other devices. As we explained then, no one knew for sure what processors WD has used for its disk and SSD controllers, though they was likely Arm-compatible chips – such as Arm9 and Cortex-M3 parts. It is known that the firm uses Intel CPUs with its ActiveScale archive systems and Tegile all-flash and hybrid arrays.
Last year, the disk and solid-state drive manufacturer vowed that RISC-V was its future, and today it announced the SweRV core, a networked cache coherency scheme, and a SweRV instruction set simulator.
[...] The SweRV core has a two-way superscalar design and is a 32-bit, nine-stage pipeline core, meaning several instructions can be loaded at once and execute simultaneously to save time. It is also an in-order core, whose relative single core performance (a simulated 4.9 CoreMark/Mhz) is expected to exceed that of many out-of-order cores, such as the Arm Cortex A15 (actual 4.72CoreMark/Mhz). Clock speeds go up to 1.8Ghz and it will be built on a
28mm[28nm] CMOS process technology.WD said it hopes open-sourcing the core will drive development of data-centric applications such as Internet of Things (IoT), secure processing, industrial controls and more. We understand WD's ambitions for using RISC-V CPUs go beyond disk and flash drive controllers.
Previously: Western Digital to Transition Consumption of Over One Billion Cores Per Year to RISC-V
Related: WD Announces Client NVMe SSDs with In-House Controllers
Western Digital's RISC-V "SweRV" Core Design Released For Free
Western Digital has published a register-transfer level (RTL) design abstraction of its in-house designed SweRV RISC-V core. The SweRV core is one of several RISC-V projects the company as undertaken as part of their effort to spearhead the ISA, its ecosystem, and foster their own transition away from licensed, royalty-charging CPU cores. In accordance with the more open design goals of RISC-V, the publication of the high-level representation of SweTV means that third parties can use it in their own chip designs, which will popularize not only the particular core design, but also the RISC-V architecture in general.
The RTL design abstraction of Western Digital's RISC-V SweRV core is now available at GitHub. The design is licensed under the Apache 2.0 license, which is a very permissive (and non-copyleft) license that allows the core to be used free of charge, with or without modifications, and without requiring any modifications to be released in-kind. In fact the requirements of the license are quite slim; besides requiring appropriate attribution, the only other notable restriction is that third party developers cannot use Western Digital's brands to mark their work.
Previously: Western Digital to Transition Consumption of Over One Billion Cores Per Year to RISC-V
Western Digital Unveils RISC-V Controller Design
UEFI Boot Support Published For RISC-V On Linux
Western Digital's Atish Patra sent out the patch series on Tuesday for adding UEFI support for the RISC-V architecture. This initial UEFI Linux bring-up is for supporting boot time services while the UEFI runtime service support is still being worked on. This RISC-V UEFI support can work in conjunction with the U-Boot bootloader and depends upon other recent Linux kernel work around RISC-V's Supervisor Binary Interface (SBI).
Building off the common (U)EFI code within the Linux kernel, the RISC-V bring-up so far is just over four hundred lines of code. Depending upon how quickly this code is reviewed, the initial UEFI RISC-V support could land for the Linux 5.7 cycle. So far this RISC-V UEFI boot support has been tested under QEMU.
Unified Extensible Firmware Interface (UEFI).
See also: Linux EFI Going Through Spring Cleaning Before RISC-V Support Lands
Related:
Western Digital to Transition Consumption of Over One Billion Cores Per Year to RISC-V
Western Digital Publishes RISC-V "SweRV" Core Design Under Apache 2.0 License
(Score: 3, Informative) by takyon on Thursday November 30 2017, @11:02AM (2 children)
How WD Plans to Lead Major Changeover to RISC-V Processing [eweek.com]
RISC-V Spins into Drives, AI [eetimes.com]
Big Tech Players Start To Adopt The RISC-V Chip Architecture [tomshardware.com]
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by JoeMerchant on Thursday November 30 2017, @12:58PM
So, I'm lazy, but... assuming they are transitioning away from ARM? Watch this space: https://finance.yahoo.com/quote/SFTBY?ltr=1 [yahoo.com] for a reaction to the news.
🌻🌻 [google.com]
(Score: 0) by Anonymous Coward on Thursday November 30 2017, @04:48PM
in the third link it said that nvidia will be moving to risk for their GPU microcontrollers. it's going to feel weird moving to all nvidia, assuming they helped more with nouveau...
(Score: 3, Interesting) by Wootery on Thursday November 30 2017, @12:02PM (12 children)
Real industry adoption, by a major player, doing mission-critical work in their core products. Great stuff.
Here's to a long and varied future of success for RISC-V. [Raises mug]
(Score: 3, Funny) by takyon on Thursday November 30 2017, @12:32PM (9 children)
Can we say "RISCY business"? "RISC-V business"?
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 1, Interesting) by Anonymous Coward on Thursday November 30 2017, @01:38PM (2 children)
"RISQUE Business"?
(Score: 2) by Wootery on Thursday November 30 2017, @02:08PM (1 child)
Eh? Is RISQUE an acronym?
(Score: 2) by DannyB on Thursday November 30 2017, @03:44PM
RISC-V Quality User Experience
RISC-V Quality Useful Exceptional
The lower I set my standards the more accomplishments I have.
(Score: 2) by Wootery on Thursday November 30 2017, @02:10PM (5 children)
Don't give them ideas - next thing we know we'll have a RISC management engine.
(Score: 4, Funny) by DannyB on Thursday November 30 2017, @03:46PM (3 children)
Maybe we do already and we just don't know it. Or maybe that's what they want you to think. Or maybe Obama's birth certificate was signed using a weak cryptographic key. Or maybe the aliens are behind it.
The lower I set my standards the more accomplishments I have.
(Score: 2) by bob_super on Thursday November 30 2017, @06:20PM (2 children)
> birth certificate was signed using a weak cryptographic key
New geek idea: The same way that nobles and Chinese people used to seal or sign stuff with custom stamps, I'm gonna get stamps made with the customer's Public Key to sign official papers, checks and letters.
Patent pending.
(Score: 2) by takyon on Thursday November 30 2017, @06:33PM (1 child)
I hope you can fit all 16,384 bits on there.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by bob_super on Thursday November 30 2017, @06:39PM
https://www.rubberstamps.net/ProductDetail.aspx?ProductID=WOODSTAMP16 [rubberstamps.net]
alternatively:
https://tufel.files.wordpress.com/2008/02/big-stamp.jpg [wordpress.com]
(Score: 2) by RamiK on Thursday November 30 2017, @08:48PM
The sanctums proposal satisfies remote computing and DRM: https://www.youtube.com/watch?v=K3EN0_g6yL4 [youtube.com]
There are recent attempts at formal verification: https://people.eecs.berkeley.edu/~rsinha/research/pubs/ccs2017.pdf [berkeley.edu]
It's basically a cleaned up SGX that could allow a per-machine key to be issued by the silicon manufacturers as a CA. But the enclave is isolated and can't access anything the OS hasn't allocated it.
The nice thing about this design is that, if you choose to, it will let you reject any enclave requests or just approve specific requests through the OS. While, at the same time, it has no persistent code running in the background that is outside your control as long as there aren't any enclaves running. This can also be verified easily by measuring power and/or thermal imaging the die while idling.
compiling...
(Score: 3, Insightful) by driverless on Friday December 01 2017, @12:49AM (1 child)
Real press release, by a major player currently renegotiating their Arm license. Commercially astute stuff.
(Score: 2) by Wootery on Friday December 01 2017, @10:34AM
Fair points, but did OpenRISC ever see this kind of success?
(Score: 2) by Rich on Thursday November 30 2017, @09:35PM
We can be happy every time such a libre solution scores a design win and gets a bit more entrenched.
I'm wondering what strings have been pulled behind the scenes. I've been dabbling in the world of DLX-descendents, particularly with a bit of work on the Microblaze Linux port for a vertical market customer, and have been aware of the developments. (To those who haven't heard of DLX or Hennessy/Patterson-Architecture, it's kind of the idea seed for the MIPS like architectures, Microblaze, OpenRISC and now RISC-V).
So there is already a libre contender in this area (OpenRISC), even being used commercially (Samsung). The RISC-V guys are late to the party. They pull an NIH (yeah, i've seen their arguments...), deliver something which looks a tad too seasoned for an academic project, and soon after score a 1bn/a units design win.
It will be interesting to watch that space.