from the is-that-a-Cray-in-your-pocket? dept.
The Snapdragon 845 is a large step in terms of SoC architectures as it's the first to employ ARM's DynamiQ CPU cluster organization. Quickly explained, DynamIQ enables the various different CPU cores within an SoC to be hosted within the same cluster and cache hierarchy, as opposed to having separate discrete clusters with no shared cache between them (with coherency instead happening over an interconnect such as ARM's CCI). This major transition is probably the largest to date that we've seen in modern mobile smartphone ARM consumer SoCs.
[...] The Kryo 385 gold/performance cluster runs at up to 2.8GHz, which is a 14% frequency increase over the 2.45GHz of the Snapdragon 835's CPU core. But we also have to remember that given that the new CPU cores are likely based on A75's we should be expecting IPC gains of up to 22-34% based on use-cases, bringing the overall expected performance improvement to 25-39%. Qualcomm promises a 25-30% increase so we're not far off from ARM's projections.
The silver/efficiency cluster is running at 1.8GHz, this is clocked slightly slower than the A53's on the Snapdragon 835 however the maximum clocks of the efficiency cluster is mainly determined by where the efficiency curve of the performance cluster intersects. Nevertheless the efficiency cores promise 15% boost in performance compared to its predecessor.
The Adreno 630 GPU should provide up to 30% better performance than the Snapdragon 835's Adreno 540 at the same level of power consumption. Snapdragon 845 devices can record (encode) 2160p60 10-bit H.265 video, compared to 2160p30 for Snapdragon 835.
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Qualcomm previously revealed the name of its new high-end SoC, but today at CES 2017 it discussed the Snapdragon 835 in greater detail. Replacing the Snapdragon 820/821 as the pinnacle processor in its lineup, the 835 is the first commercial SoC to use Samsung's 10nm "10LPE" FinFET manufacturing node. Qualcomm did not disclose die size, but it said the overall package size is 35% smaller than the Snapdragon 820 and contains more than 3 billion transistors. Samsung says its third-generation FinFET node "allows up to a 30% increase in area efficiency with 27% higher performance or up to 40% lower power consumption" relative to its first-generation 14nm 14LPE node at the same frequency, so Snapdragon 835's process advantage over the 820, which uses Samsung's second-generation 14LPP node, will be a bit less.
[...] Qualcomm finds itself in a much different position today compared to one year ago when it launched the Snapdragon 820. Back then, it was on the hot seat after its previous flagship products, the Snapdragon 808 and 810, failed to meet expectations. Qualcomm's implementation of ARM's Cortex-A57 CPU core and TSMC's last 20nm planar process were not a good combination, resulting in a generation of flagship phones that struggled to meet or exceed the performance of older models and exhibited higher than normal skin temperatures. The success of Snapdragon 820 would be crucial to regaining its partner's trust and restoring its image with consumers. The 820 was pivotal for another reason too: It introduced Qualcomm's first custom 64-bit CPU core, Kryo. Creating a custom CPU (or GPU/DSP/ISP) is one way for SoC vendors to differentiate their products and establish themselves as innovators. Snapdragon 810's use of stock ARM cores could be construed as a step backwards then after previous Snapdragon SoCs used Qualcomm's custom Krait CPUs. Apple's prior introduction of a custom 64-bit CPU, which caught everyone by surprise, only added fuel to the fire.
ARM will replace the big.LITTLE cluster design with a new one that allows up to 8 CPU cores per cluster, different types of cores within a cluster, and anywhere from one to many (unlimited?) clusters:
The first stage of DynamIQ is a larger cluster paradigm - which means up to eight cores per cluster. But in a twist, there can be a variable core design within a cluster. Those eight cores could be different cores entirely, from different ARM Cortex-A families in different configurations.
Many questions come up here, such as how the cache hierarchy will allow threads to migrate between cores within a cluster (perhaps similar to how threads migrate between clusters on big.Little today), even when cores have different cache arrangements. ARM did not yet go into that level of detail, however we were told that more information will be provided in the coming months.
Each variable core-configuration cluster will be a part of a new fabric, with uses additional power saving modes and aims to provide much lower latency. The underlying design also allows each core to be controlled independently for voltage and frequency, as well as sleep states. Based on the slide diagrams, various other IP blocks, such as accelerators, should be able to be plugged into this fabric and benefit from that low latency. ARM quoted elements such as safety critical automotive decisions can benefit from this.
A tri-cluster smartphone design using 2 high-end cores, 2 mid-level cores, and 4 low-power cores could be replaced by one that uses all three types of core in the same single cluster. The advantage of that approach remains to be seen.
More about ARM big.LITTLE.