from the progress++ dept.
An Intel website leaked some details of the Intel Core i7-8809G, a "Kaby Lake" desktop CPU with on-package AMD Radeon graphics and High Bandwidth Memory 2.0. While it is listed as an 8th-generation part, 8th-generation "Coffee Lake" CPUs for desktop users have up to 6 cores (in other words, Intel has been releasing multiple microarchitectures as "8th-generation"). The i7-8809G may be officially announced at the Consumer Electronics Show next week.
The components are linked together using what Intel calls "embedded multi-die interconnect bridge technology" (EMIB). The thermal design power (TDP) of the entire package is around 100 Watts:
Intel at the original launch did state that they were using Core-H grade CPUs for the Intel with Radeon Graphics products, which would mean that the CPU portion is around 45W. This would lead to ~55W left for graphics, which would be in the RX 550 level: 8 CUs, 512 SPs, running at 1100 MHz. It is worth nothing that AMD already puts up to 10 Vega CUs in its 15W processors, so with the Intel i7-8809G product Intel has likely has gone wider and slower: judging by the size of the silicon in the mockup, this could be more of a 20-24 CU design built within that 55W-75W window, depending on how the power budget is moved around between CPU and GPU. We await more information, of course.
It is rumored to include 4 GB of HBM2 on-package, while the CPU also supports DDR4-2400 memory. Two cheaper EMIB CPUs have been mentioned:
According to some other media, the 8809G will turbo to 4.1 GHz, while the graphics will feature 24 [compute units (CUs)] (1536 [stream processors (SPs)]) running at 1190 MHz while the HBM2 is 4GB and will run at 800 MHz. The same media are also listing the Core i7-8705G (20 CUs, 1000 MHz on 'Vega M GL', 700 MHz on HBM2) and a Core i7-8706G. None of the information from those sources is yet to be verified by AnandTech or found on an official Intel webpage.
Currently available AMD Ryzen Mobile APUs only include 8-10 Vega CUs. These are mobile chips with a maximum TDP of 25 W; no desktop Ryzen chips with integrated graphics have been announced yet.
the new processor integrates a "semi-custom" AMD graphics chip and the second generation of Intel's "High Bandwidth Memory (HBM2)", which is comparable to GDDR5 in a traditional laptop.
Intel CPU and AMD GPU, together at last
Summary of Intel's news:
The new product, which will be part of our 8th Gen Intel Core family, brings together our high-performing Intel Core H-series processor, second generation High Bandwidth Memory (HBM2) and a custom-to-Intel third-party discrete graphics chip from AMD's Radeon Technologies Group* – all in a single processor package.
[...] At the heart of this new design is EMIB (Embedded Multi-Die Interconnect Bridge), a small intelligent bridge that allows heterogeneous silicon to quickly pass information in extremely close proximity. EMIB eliminates height impact as well as manufacturing and design complexities, enabling faster, more powerful and more efficient products in smaller sizes. This is the first consumer product that takes advantage of EMIB.
[...] Additionally, this solution is the first mobile PC to use HBM2, which consumes much less power and takes up less space compared to traditional discrete graphics-based designs using dedicated graphics memory, like GDDR5 memory.
takyon: This is more like an "integrated discrete GPU" than standard integrated graphics. It also avoids the need for Intel to license AMD's IP. AMD also needs to make a lot of parts since its wafer supply agreement with GlobalFoundries penalizes AMD if they buy less than a target number of wafers each year.
At the Consumer Electronics Show, AMD confirmed details about products coming out in 2018:
- Ryzen 3 Mobile APUs: January 9th
- Ryzen Desktop APUs: February 12th
- Second Generation Ryzen Desktop Processors: April.
- Ryzen Pro Mobile APUs: Q2 2018
- Second Generation Threadripper Processors: 2H 2018
- Second Generation Ryzen Pro Desktop Processors: 2H 2018
The second generation "Zen+" products use a "12nm" process. Zen 2 and Zen 3 will use a "7nm" and "7nm+" process and will be out around 2019-2020.
Two cheaper Ryzen-based mobile APUs have been released. The Ryzen 3 2300U has 4 cores, 4 threads, and the Ryzen 3 2200U has 2 cores, 4 threads, making it the first dual-core part in the entire Ryzen product line. All of the Ryzen mobile parts have a 15 W TDP so far.
AMD has also lowered the suggested pricing for many of its Ryzen CPUs. For example, $299 for Ryzen 7 1700 from $329. The Threadripper Ryzen TR 1900X is down to $449 from $549.
Intel has officially launched five new Kaby Lake CPUs with AMD Radeon Vega graphics and 4 GB of High Bandwidth Memory. Each CPU also includes Intel's HD 630 GT2 integrated graphics, which is expected to be used for lower power video encode/decode tasks.
Intel will be using a few packaging technologies to connect CPU core "chiplets":
Intel revealed three new packaging technologies at SEMICON West: Co-EMIB, Omni-Directional Interconnect (ODI) and Multi-Die I/O (MDIO). These new technologies enable massive designs by stitching together multiple dies into one processor. Building upon Intel's 2.5D EMIB and 3D Foveros tech, the technologies aim to bring near-monolithic power and performance to heterogeneous packages. For the data-center, that could enable a platform scope that far exceeds the die-size limits of single dies.
[...] Compared to interposers, which can be reticle-sized (832mm2) or even larger, [EMIB (Embedded Multi-die Interconnect Bridge)] is just a small (hence, cheap) piece of silicon. It provides the same bandwidth and energy-per-bit advantages of an interposer compared to standard package traces, which are traditionally used for multi-chip packages (MCPs), such as AMD's Infinity Fabric. (To some extent, because the PCH is a separate die, chiplets have actually been around for a very long time.)
[...] Intel showed off a concept product that contains four Foveros stacks, with each stack having eight small compute chiplets that are connected via TSVs to the base die. (So the role of Foveros there is to connect the chiplets as if it were a monolithic die.) Each Foveros stack is then interconnected via two (Co-)EMIB links with its two adjacent Foveros stacks. Co-EMIB is further used to connect the HBM and transceivers to the compute stacks.
Evidently, the cost of such a product would be enormous, as it essentially contains multiple traditional monolithic-class products in a single package. That's likely why Intel categorized it as a data-centric concept product, aimed mainly at the cloud players that are more than happy to absorb those costs in exchange for the extra performance.
[...] When they are ready, these technologies will provide Intel with powerful capabilities for the heterogeneous and data-centric era. On the client side, the benefits of advanced packaging include smaller package size and lower power consumption (for Lakefield, Intel claims a 10x SoC standby power improvement at 2.6mW). In the data center, advanced packaging will help to build very large and powerful platforms on a single package, with performance, latency, and power characteristics close to what a monolithic die would yield. The yield advantage of small chiplets and the establishment of chipset ecosystem are major drivers, too.
Related: Intel Core i7-8809G with Radeon Graphics and High Bandwidth Memory: Details Leaked
Intel Announces "Sunny Cove", Gen11 Graphics, Discrete Graphics Brand Name, 3D Packaging, and More
Intel Promises "10nm" Chips by the End of 2019, and More
Intel Details Lakefield CPU SoC With 3D Packaging and Big/Small Core Configuration
Intel's Jim Keller Promises That "Moore's Law" is Not Dead, Outlines 50x Improvement Plan
Samsung has developed the first 12-layer High Bandwidth Memory stacks:
Samsung's 12-layer DRAM KGSDs (known good stack die) will feature 60,000 [through silicon via (TSV)] holes which is why the manufacturer considers its technology one of the most challenging packaging for mass production. Despite increase of the number of layers from eight to 12, thickness of the package will remain at 720 microns, so Samsung's partners will not have to change anything on their side to use the new technology. It does mean that we're seeing DRAM layers getting thinner, with acceptable yields for high-end products.
One of the first products to use Samsung's 12-layer DRAM packaging technology will be the company's 24 GB HBM2 KGSDs that will be mass produced shortly. These devices will allow developers of CPUs, GPUs, and FPGAs to install 48 GB or 96 GB of memory in case of 2048 or 4096-bit buses, respectively. It also allows for 12 GB and 6 GB stacks with less dense configurations.
"12-Hi" stacks were added to the HBM2 standard back in December, but there were no immediate plans by Samsung or SK Hynix to manufacture it.
Future AMD CPUs (particularly Epyc) may feature HBM stacks somewhere on the CPU die. Intel has already used its embedded multi-die interconnect bridge (EMIB) technology with HBM to create an advanced APU with AMD's own graphics, and is using HBM on field programmable gate arrays (FPGAs) and other products.
AMD's Radeon VII GPU has 16 GB of HBM2. Nvidia's V100 GPU has 16 or 32 GB on a 4,096-bit memory bus.
Also at Electronics Weekly.