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posted by martyb on Thursday January 18 2018, @12:54PM   Printer-friendly
from the gonna-need-ultra-thin-cooling dept.

Engineers worldwide have been developing alternative ways to provide greater memory storage capacity on even smaller computer chips. Previous research into two-dimensional atomic sheets for memory storage has failed to uncover their potential -- until now.

A team of electrical engineers at The University of Texas at Austin, in collaboration with Peking University scientists, has developed the thinnest memory storage device with dense memory capacity, paving the way for faster, smaller and smarter computer chips for everything from consumer electronics to big data to brain-inspired computing.

"For a long time, the consensus was that it wasn't possible to make memory devices from materials that were only one atomic layer thick," said Deji Akinwande, associate professor in the Cockrell School of Engineering's Department of Electrical and Computer Engineering. "With our new 'atomristors,' we have shown it is indeed possible."

Made from 2-D nanomaterials, the "atomristors" -- a term Akinwande coined -- improve upon memristors, an emerging memory storage technology with lower memory scalability. He and his team published their findings in the January issue of Nano Letters.

"Atomristors will allow for the advancement of Moore's Law at the system level by enabling the 3-D integration of nanoscale memory with nanoscale transistors on the same chip for advanced computing systems," Akinwande said.

Source:https://www.sciencedaily.com/releases/2018/01/180117114918.htm

Journal Reference:

Ruijing Ge, Xiaohan Wu, Myungsoo Kim, Jianping Shi, Sushant Sonde, Li Tao, Yanfeng Zhang, Jack C. Lee, Deji Akinwande. Atomristor: Nonvolatile Resistance Switching in Atomic Sheets of Transition Metal Dichalcogenides. Nano Letters, 2017; 18 (1): 434 DOI: 10.1021/acs.nanolett.7b04342


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  • (Score: 2) by takyon on Thursday January 18 2018, @01:24PM (2 children)

    by takyon (881) <takyonNO@SPAMsoylentnews.org> on Thursday January 18 2018, @01:24PM (#624119) Journal

    When will memory stacked on processors become standard?

    https://www.sigarch.org/die-stacking-is-happening/ [sigarch.org]

    It will probably be mainstream before "atomristors" are ready.

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    • (Score: 2) by bob_super on Thursday January 18 2018, @05:10PM (1 child)

      by bob_super (1357) on Thursday January 18 2018, @05:10PM (#624217)

      > memory stacked on processors

      Not "on", but "next to".
      Processor performance is (almost) always limited by heat removal, and also by interface speeds. Put memory under (from a package standpoint) and you'll slow the pins, put memory above and you'll slow heat transfer.

      • (Score: 2) by takyon on Thursday January 18 2018, @10:00PM

        by takyon (881) <takyonNO@SPAMsoylentnews.org> on Thursday January 18 2018, @10:00PM (#624425) Journal

        It's nevertheless the first thing that is likely to get stacked on the CPU, long before other CPU cores get stacked on top (which is a goal for the industry).

        Kaby Lake with AMD graphics [anandtech.com] does it like you suggest, adding 4 GB of High Bandwidth Memory on the same chip but off to the side. On the other hand, Intel Knights Landing Xeon Phi chips have 16 GiB of MCDRAM sitting on top [intel.com] of the processor. And the TDPs of those chips [wikipedia.org] range from 215 W to 260 W... quite hot.

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  • (Score: 2) by anotherblackhat on Thursday January 18 2018, @02:22PM (3 children)

    by anotherblackhat (4722) on Thursday January 18 2018, @02:22PM (#624134)

    Moore's law says the number of transistors on a chip doubles every two years.
    Prior to "3D" circuits, that meant for the same cost you could get twice as many transistors.
    Making chips is still basically a printing process, and most of the costs are in "printing" the layers, not the substrate.

    Stacking layers improves transistors/m2, but it doesn't improve transistors/$.

    • (Score: 3, Interesting) by takyon on Thursday January 18 2018, @02:47PM (2 children)

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Thursday January 18 2018, @02:47PM (#624146) Journal

      96-layer NAND [wikipedia.org] has been announced [wdc.com], 128+ layers are coming. Although these use older, larger, and cheaper process nodes, a hundred layer device is not 100x as costly. Maybe string stacking [theregister.co.uk] two dies could double the cost.

      Even if we only end up getting an improvement in transistors/m2, that's still a valuable improvement for those who demand the density (at "any" cost).

      Finally, this thing isn't made of transistors. It's not much different than stacking MCDRAM or High Bandwidth Memory on top of the CPU. Stacked CPU cores are still stuck in the lab, but necessary if we want to continue Moore's law in terms of transistors/m2.

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      • (Score: 2) by anotherblackhat on Thursday January 18 2018, @03:39PM

        by anotherblackhat (4722) on Thursday January 18 2018, @03:39PM (#624169)

        ...a hundred layer device is not 100x as costly.

        Stacking is an improvement, no argument there, and yes density matters, but...
        While 100x isn't 100 times as costly as 1x,
        100x is pretty close to twice as costly as 50x.

        Point being, stacking offers a diminishing improvement.
        Moore's law is an exponential improvement.

      • (Score: 2) by HiThere on Thursday January 18 2018, @06:17PM

        by HiThere (866) Subscriber Badge on Thursday January 18 2018, @06:17PM (#624259) Journal

        IIUC, though, those are devices that don't require power to stay in operation. Like flash or core memory. That kind of device doesn't have the same heat extraction limit as do dynamic devices.

        OTOH, this suggests a stack of static memory with a dynamic CPU built on top of it. Get this down to atomic scale (well, nano-scale, but they're calling the things atomistors) and you're coming reasonably close to "computronium". But for this to work you really need to get your defect count down. The summary also doesn't talk about speed, so I'm going to guess that it's not extremely fast memory. Short transmission paths make up for a lot, but device speed can still dominate.

        So what I'm seeing is the promise of "grain of rice" or even "mustard seed" sized controllers for IoT devices. Quite important, but not exactly something I'm looking forwards to. And 15-20 years from now.

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