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posted by martyb on Friday March 02 2018, @07:55AM   Printer-friendly
from the small-details dept.

Imec and Cadence Tape Out Industry's First 3nm Test Chip

The world-leading research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. today announced that its extensive, long-standing collaboration has resulted in the industry's first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.

A tape-out is the final step before the design is sent to be fabricated.

Meanwhile, Imec is looking towards nodes smaller than "3nm":

[...] industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, according to the International Technology Roadmap for Semiconductors (ITRS) version 2.0. Another organization, Imec, is more aggressive with the timetable, saying that 2.5nm or thereabouts will arrive by 2024.

Also at EE Times.

Related: TSMC Plans New Fab for 3nm
Samsung Plans a "4nm" Process
IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020


Original Submission

Related Stories

Samsung Plans a "4nm" Process 12 comments

Samsung has added a so-called "4nm" process to its roadmap:

At the annual Samsung Foundry Forum, Samsung announced its foundry's roadmap for the next few years, which includes an 18nm FD-SOI [(Fully Depleted – Silicon on Insulator)] generation targeting low-cost IoT chips as well as 8nm, 7nm, 6nm, 5nm, and even 4nm process generations.

[...] 7LPP (7nm Low Power Plus): 7LPP will be the first semiconductor process technology to use an EUV lithography solution. 250W of maximum EUV source power, which is the most important milestone for EUV insertion into high volume production, was developed by the collaborative efforts of Samsung and ASML. EUV lithography deployment will break the barriers of Moore's law scaling, paving the way for single nanometer semiconductor technology generations.

[...] The 4LPP process generation will be Samsung's first to use a "Gate All Around FET" (GAAFET) transistor structure, with Samsung's own implementation dubbed "Multi Bridge Channel FET" (MBCFET). The technology uses a "Nanosheet" device to overcome the physical limitations of the FinFET architecture.

Source.

But how many transistors per square millimeter is it?


Original Submission

IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors 10 comments

IBM, which demonstrated the world's first 7nm process silicon chip in 2015, has followed up at the 5nm node. Extreme ultraviolet lithography was required:

IBM, working with Samsung and GlobalFoundries, has unveiled the world's first 5nm silicon chip. Beyond the usual power, performance, and density improvement from moving to smaller transistors, the 5nm IBM chip is notable for being one of the first to use horizontal gate-all-around (GAA) transistors, and the first real use of extreme ultraviolet (EUV) lithography.

GAAFETs are the next evolution of tri-gate finFETs: finFETs, which are currently used for most 22nm-and-below chip designs, will probably run out of steam at around 7nm; GAAFETs may go all the way down to 3nm, especially when combined with EUV. No one really knows what comes after 3nm.

[...] One major advantage of IBM's 5nm GAAFETs is a significant reduction in patterning complexity. Ever since we crossed the 28nm node, chips have become increasingly expensive to manufacture, due to the added complexity of fabricating ever-smaller features at ever-increasing densities. Patterning is the multi-stage process where the layout of the chip—defining where the nanosheets and other components will eventually be built—is etched using a lithographic process. As features get smaller and more complex, more patterning stages are required, which drives up the cost and time of producing each wafer.

[...] IBM says that, compared to commercial 10nm chips (presumably Samsung's 10nm process), the new 5nm tech offers a 40 percent performance boost at the same power, or a 75 percent drop in power consumption at the same performance. Density is also through the roof, with IBM claiming it can squeeze up to 30 billion transistors onto a 50-square-millimetre chip (roughly the size of a fingernail), up from 20 billion transistors on a similarly-sized 7nm chip.

Press release. Also at The Verge, TechCrunch, EE Times, PCMag, and CNET.

Related:
Samsung Plans a "4nm" Process


Original Submission

GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm 9 comments

GlobalFoundries: Next-generation chip factories will cost at least $10 billion

The economics of the chip industry are pretty staggering. Sanjay Jha, CEO of contract chip manufacturer Globalfoundries, recently told me that it could cost between $10 billion and $12 billion to build a next-generation chip factory based on the latest technology, dubbed 7-nanometer production. And one for the generation after that, dubbed 5-nanometer production, could cost $14 billion to $18 billion.

There are only a few companies in the world that can afford to spend that much money on a chip factory. And they can do it because those chips are expected to generate billions of dollars in revenue over the life of the factory.

Dean Takahashi from VentureBeat interviewed Sanjay Jha, CEO of GlobalFoundries:

Basically, the numbers don't mean much these days. I think Samsung has talked about 10nm, 11nm, 14nm, 8nm, 7nm, 6nm. I don't know what they mean. The way to think about 12nm is it has higher performance and more scale than 14nm. It's not quite the scaling or performance of 10nm. Performance may be very close to 10nm, though.

TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020 3 comments

Taiwan Semiconductor Manufacturing Company (TSMC) plans to make so-called "5nm" chips starting in early 2020:

TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC's 5 nm process starting from early 2020. When all three phases of the manufacturing facility are completed, its wafer starts capacity will exceed one million 300-mm wafers per year, comparable with other three GigaFabs operated by TSMC.

TSMC's Fab 18 will be located in Tainan (in the Southern Taiwan Science Park), and will be built in three phases. The construction of the first phase or segment of the building will be completed in about a year from now, after which TSMC will move in equipment sometime in early 2019. In about two years from now, the company expects to start volume production of chips using its 5 nm process technology at the Fab 18/phase 1. Construction of the second and the third phases will commence in Q3 2018 and Q3 2019. The two phases will start volume production in 2020 and 2021, respectively.

Extreme ultraviolet (EUV) lithography could be used to make "7nm" chips, but not "5nm" yet.

Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm


Original Submission

Samsung Roadmap Includes "5nm", "4nm" and "3nm" Manufacturing Nodes 10 comments

Samsung has replaced planned "6nm" and "5nm" nodes with a new "5nm" node on its roadmap, and plans to continue scaling down to "3nm", which will use gate-all-around transistors instead of Fin Field-effect transistors. Extreme ultraviolet lithography (EUV) will be required for everything below "7nm" (TSMC and GlobalFoundries will start producing "7nm" chips without EUV initially):

Last year Samsung said that its 7LPP manufacturing technology will be followed up by 5LPP and 6LPP in 2019 (risk production). The new roadmap does not mention either processes, but introduces the 5LPE (5 nm low power early) that promises to "allow greater area scaling and ultra-low power benefits" when compared to 7LPP. It is unclear when Samsung plans to start using 5LPE for commercial products, but since it is set to replace 7LPP, expect the tech to be ready for risk production in 2019.

[...] Samsung will have two 4 nm process technologies instead of one — 4LPE and 4LPP. Both will be based on proven FinFETs and usage of this transistor structure is expected to allow timely ramp-up to the stable yield level. Meanwhile, the manufacturer claims that their 4 nm nodes will enable higher performance and geometry scaling when compared to the 5LPE, but is not elaborating beyond that (in fact, even the key differences between the three technologies are unclear). Furthermore, Samsung claims that 4LPE/4LPP will enable easy migration from 5LPE, but is not providing any details.

[...] The most advanced process technologies that Samsung announced this week are the 3GAAE/GAAP (3nm gate-all-around early/plus). Both will rely on Samsung's own GAAFET implementation that the company calls MBCFET (multi-bridge-channel FETs), but again, Samsung is not elaborating on any details. The only thing that it does say is that the MBCFET has been in development since 2002, so it will have taken the tech at least twenty years to get from an early concept to production.

MBCFETs are intended to enable Samsung to continue increasing transistor density while reducing power consumption and increasing the performance of its SoCs. Since the 3GAAE/GAAP technologies are three or four generations away, it is hard to make predictions about their actual benefits. What is safe to say is that the 3GAAE will be Samsung's fifth-generation EUV process technology and therefore will extensively use appropriate tools. Therefore, the success of the[sic] EUV in general will have a clear impact on Samsung's technologies several years down the road.

Previously: Samsung Plans a "4nm" Process

Related: IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process


Original Submission

GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack 15 comments

GlobalFoundries has halted development of its "7nm" low power node, will fire 5% of its staff, and will also halt most development of smaller nodes (such as "5nm" and "3nm"):

GlobalFoundries on Monday announced an important strategy shift. The contract maker of semiconductors decided to cease development of bleeding edge manufacturing technologies and stop all work on its 7LP (7 nm) fabrication processes, which will not be used for any client. Instead, the company will focus on specialized process technologies for clients in emerging high-growth markets. These technologies will initially be based on the company's 14LPP/12LP platform and will include RF, embedded memory, and low power features. Because of the strategy shift, GF will cut 5% of its staff as well as renegotiate its WSA and IP-related deals with AMD and IBM. In a bid to understand more what is going on, we sat down with Gary Patton, CTO of GlobalFoundries.

[...] Along with the cancellation of the 7LP, GlobalFoundries essentially canned all pathfinding and research operations for 5 nm and 3 nm nodes. The company will continue to work with the IBM Research Alliance (in Albany, NY) until the end of this year, but GlobalFoundries is not sure it makes sense to invest in R&D for 'bleeding edge' nodes given that it does not plan to use them any time soon. The manufacturer will continue to cooperate with IMEC, which works on a broader set of technologies that will be useful for GF's upcoming specialized fabrication processes, but obviously it will refocus its priorities there as well (more on GF's future process technologies later in this article).

So, the key takeaway here is that while the 7LP platform was a bit behind TSMC's CLN7FF when it comes to HVM – and GlobalFoundries has never been first to market with leading edge bulk manufacturing technologies anyway – there were no issues with the fabrication process itself. Rather there were deeper economic reasons behind the decision.

GlobalFoundries would have needed to use deep ultraviolet (DUV) instead of extreme ultraviolet (EUV) lithography for its initial "7nm" chips. It would have also required billions of dollars of investment to succeed on the "7nm" node, only to make less "7nm" chips than its competitors. The change in plans will require further renegotiation of GlobalFoundries' and AMD's Wafer Supply Agreement (WSA).

Meanwhile, AMD will move most of its business over to TSMC, although it may consider using Samsung:

TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April 13 comments

TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019

Last week, TSMC made two important announcements concerning its progress with extreme ultraviolet lithography (EUVL). First up, the company has successfully taped out its first customer chip using its second-generation 7 nm process technology, which incorporates limited EUVL usage. Secondly, TSMC disclosed plans to start risk production of 5 nm devices in April.

TSMC initiated high-volume manufacturing of chips using its first generation 7 nm fabrication process (CLN7FF, N7) in April. N7 is based around deep ultraviolet (DUV) lithography with ArF excimer lasers. By contrast, TSMC's second-generation 7 nm manufacturing technology (CLN7FF+, N7+) will use extreme ultraviolet lithography for four non-critical layers, mostly in a bid to speed up production and learn how to use ASML's Twinscan NXE step-and-scan systems for HVM. Factual information on the improvements from N7 to N7+ are rather limited: the new tech will offer a 20% higher transistor density (because of tighter metal pitch) and ~8% lower power consumption at the same complexity and frequency (between 6% and 12% to be more precise).

[...] After N7+ comes TSMC's first-generation 5 nm (CLN5FF, N5) process, which will use EUV on up to 14 layers. This will enable tangible improvements in terms of density, but will require TSMC to extensively use EUV equipment. When compared to TSMC's N7, N5 technology will enable TSMC's customers to shrink area of their designs by ~45% (i.e. transistor density of N5 is ~1.8x higher than that of N7), increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction[sic] (at the same frequency and complexity).

TSMC will be ready to start risk production of chips using its N5 tech in April, 2019. Keeping in mind that it typically takes foundries and their customers about a year to get from risk production to HVM, it seems like TSMC is on-track for mass production of 5 nm chips in Q2 2020, right in time to address smartphones due in the second half of 2020.

Tape-out. Risk production = early production.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process

Related: TSMC to Build 7nm Process Test Chips in Q1 2018
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Will Make AMD's "7nm" Epyc Server CPUs
GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack


Original Submission

IMEC and GlobalFoundries Demonstrate Processor-in-Memory Efficiency Breakthrough 10 comments

Imec Develops Efficient Processor In Memory Technique for GloFo

Imec and GlobalFoundries have demonstrated a processor-in-memory chip that can achieve energy efficiency up to 2900 TOPS/W, approximately two orders of magnitude above today's commercial processor-in-memory chips. The chip uses an established idea, analog computing, implemented in SRAM in GlobalFoundries' 22nm fully-depleted silicon-on-insulator (FD-SOI) process technology. Imec's analog in-memory compute (AiMC) will be available to GlobalFoundries customers as a feature that can be implemented on the company's 22FDX platform.

Since a neural network model may have tens or hundreds of millions of weights, sending data back and forth between the memory and the processor is inefficient. Analog computing uses a memory array to store the weights and also perform multiply-accumulate (MAC) operations, so there is no memory-to-processor transfer needed. Each memristor element (perhaps a ReRAM cell) has its conductance programmed to an analog level which is proportional to the required weight.

[...] Imec has built a test chip, called analog inference accelerator (AnIA), based on GlobalFoundries' 22nm FD-SOI process. AnIA's 512k array of SRAM cells plus digital infrastructure including 1024 DACs and 512 ADCs takes up 4mm2. It can perform around half a million computations per operation cycle based on 6-bit (plus sign bit) input activations, ternary weights (-1, 0, +1) and 6-bit outputs.

[...] Imec showed accuracy results for object recognition inference on the CIFAR 10 dataset which dropped only one percentage point compared to a similarly quantised baseline. With a supply voltage of 0.8 V, AnIA's energy efficiency is between 1050 and 1500 TOPS/W at 23.5 TOPS. For 0.6 V supply voltage, AnIA achieved 5.8 TOPS at around 1800-2900 TOPS/W.

Promising application: edge computing facial recognition cameras for the surveillance state.

Also at Wccftech.

See also: Week In Review: Auto, Security, Pervasive Computing

Previously: IBM Reduces Neural Network Energy Consumption Using Analog Memory and Non-Von Neumann Architecture

Related: "3nm" Test Chip Taped Out by Imec and Cadence
GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack - "The manufacturer will continue to cooperate with IMEC, which works on a broader set of technologies that will be useful for GF's upcoming specialized fabrication processes..."
Radar for Your Wrist


Original Submission

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  • (Score: 2) by FatPhil on Friday March 02 2018, @09:21AM (10 children)

    by FatPhil (863) <{pc-soylent} {at} {asdf.fi}> on Friday March 02 2018, @09:21AM (#646294) Homepage
    "7um", "5um", "3um", etc. are the biggest lie in the tech industry today (apart from the 'S' in 'HTTPS', snigger). Your "3um" will probably have gates that are 40um in size. Think "2um" is 5 times as good as "10um"? Think again - it's not even twice as dense (in each dimension).
    --
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    • (Score: 1, Insightful) by Anonymous Coward on Friday March 02 2018, @11:04AM (7 children)

      by Anonymous Coward on Friday March 02 2018, @11:04AM (#646315)

      nm, not um.

      Anyway, the message remains the same: shrinking continues. People in the industry know exactly what this means and does not mean, while any uneducated "Joe Random Smith" couldn't care less about the difference between feature sizes and gate sizes.

      • (Score: 2) by VLM on Friday March 02 2018, @01:48PM (5 children)

        by VLM (445) on Friday March 02 2018, @01:48PM (#646346)

        shrinking continues

        Sure about that? Its not really an engineering thing, any more than the conversion of K M G from powers of two to powers of ten was an actual improvement but was instead a marketing thing. I'm cynical enough about modern marketing to suspect that no, there isn't "shrinking continues" not at the rate you're thinking, and possibly the projected 2.5 and 1.5 processes are just going to be cherry picked marketing scams.

        Instead of theoretical artwork, show me the measured lower capacitance / higher Ft specs of the transistors... then I'll believe it. Till then, I can draw creative pictures of imaginary "moon rockets" as well as they can.

        The first derivative is still positive, however small its becoming, I'm not claiming its flatlined or negative, not yet, but that day is surely coming and its gonna hit zero sooner or later. Thats an interesting story.

        • (Score: 0) by Anonymous Coward on Friday March 02 2018, @03:29PM (3 children)

          by Anonymous Coward on Friday March 02 2018, @03:29PM (#646416)

          Sure the day is coming... Can't have 0-atoms wide wires.
          But it has not come yet.

          Warning/Disclosure: I worked at Imec for more than 15 years as a researcher (not a marketeer, mind you), so I'll claim some knowledge of the topic.

          • (Score: 2) by takyon on Friday March 02 2018, @05:11PM (2 children)

            by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday March 02 2018, @05:11PM (#646482) Journal

            We can go smaller than 0.1 atoms!

            http://hplusmagazine.com/2011/11/01/femtocomputing/ [hplusmagazine.com]

            But in seriousness, there are a number of paths to better hardware "performance" (what that actually means can vary if new forms of computing are used):

            • We scale as much as possible, below even 1.5nm, down to the neighborhood of 0.5nm and individual atoms.
            • A new material could raise clock speeds. That might require a massive increase in core count to remain physically possible.
            • Switch to photonic for everything on the chip, including transistors.
            • Stacks. Stacks for days. With 3D NAND, we've proven that transistors can be stacked in a commercial product. If there's a way to stack tens of thousands of cores and have 100% of them operating at a given time, it will be found.
            • Focus on a new type of computing, such as quantum, AI/tensor/machine learning, or neuromorphic. SoCs are already starting to include an AI chip alongside CPU and GPU. It would be interesting to see all 5 come in one system. Neuromorphic is supposed to be low power so it could be stacked more easily than a traditional CPU and quickly reach brain-like density and enable "strong AI".
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            [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
            • (Score: 2) by frojack on Friday March 02 2018, @07:38PM (1 child)

              by frojack (1554) Subscriber Badge on Friday March 02 2018, @07:38PM (#646573) Journal

              Yet just a few years ago (2012) we were assured by industry experts that 22nm was reaching a dead end, and any hope of 14 was delusional thinking and of course Moore's Law was dead.
              In 2014 the impossible 14nm appeared in commercial quantities. iPhones got thinner.l
              Experts once again gave scientific sounding explanations why this was it, the end of the die shrinkage was reached.

              --
              No, you are mistaken. I've always had this sig.
        • (Score: 2) by takyon on Friday March 02 2018, @04:53PM

          by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday March 02 2018, @04:53PM (#646472) Journal

          Well, the transistors per mm2 continues to rise with new processes. It would be nice if numbers like that were provided in every press release about "Xnm", but whatever.

          Check out the first and second graphs here:

          https://seekingalpha.com/article/4151376-tsmc-intel-lead-semiconductor-processes?page=2 [seekingalpha.com]

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          [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
      • (Score: 2) by FatPhil on Friday March 02 2018, @02:24PM

        by FatPhil (863) <{pc-soylent} {at} {asdf.fi}> on Friday March 02 2018, @02:24PM (#646366) Homepage
        The industry think that people are interested in the numbers, because they've been created purely for marketting purposes, not anything else.
        --
        Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves
    • (Score: 1) by GDX on Saturday March 03 2018, @01:52AM (1 child)

      by GDX (1950) on Saturday March 03 2018, @01:52AM (#646764)

      They're not a lie per se, actually that was never the size of the transistor but was supposed to meant the size of the finest detail that can be produced with the lithography, then the real world limitations starts. At first the node reductions reduced the chips more but now that the nodes are approaching the physical limits those physics in the real world start to make the lithography more complex due to leakage, unwanted capacitance, traces coupling, electron migration... also there is the problem with scaling the node to production and the minimal size of a working transistor that can be effectively made. This limitations are actually akin to monitor resolution, you can increase resolution to cram more text but there is a limit for the minimal text size that can be read at a given distance.

      • (Score: 2) by FatPhil on Saturday March 03 2018, @08:23AM

        by FatPhil (863) <{pc-soylent} {at} {asdf.fi}> on Saturday March 03 2018, @08:23AM (#646936) Homepage
        They are a lie. They are not linear, but they are presented with a linear unit. Therefore they must be a lie, even if at one point the numeric value coincided with something that was measurable. (Which happened about 15 or so years ago.)
        --
        Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves
  • (Score: 2) by fritsd on Friday March 02 2018, @05:05PM (1 child)

    by fritsd (4586) on Friday March 02 2018, @05:05PM (#646477) Journal

    I wonder if they're one day going to rename this technology from 3nm to 30 Ångström [wikipedia.org] .. The traditional unit for chemical bond lengths.

    30 Å chips, that's 27 Si atoms/transistor, if they're a covalent bond distance of 1.11 Å apart. Right? Oh no wait, 2 radii between 2 atoms, so make that 13 atoms / transistor.

    • (Score: 2) by frojack on Friday March 02 2018, @07:43PM

      by frojack (1554) Subscriber Badge on Friday March 02 2018, @07:43PM (#646579) Journal

      So board level component repair skilz are no good on my resume then?

      --
      No, you are mistaken. I've always had this sig.
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