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posted by janrinok on Sunday May 13 2018, @08:14AM   Printer-friendly

TSMC Details 5 nm Process Tech: Aggressive Scaling, But Thin Power and Performance Gains

At a special event last week, TSMC announced the first details about its 5 nm manufacturing technology that it plans to use sometime in 2020. CLN5 will be the company's second fabrication process to use extreme ultraviolet (EUV) lithography, which is going to enable TSMC to aggressively increase its transistor density versus prior generations. However, when it comes to performance and power improvements, the gains do not look very significant.

Just like other fabs, TSMC will gradually ramp up usage of ASML's Twinscan NXE:3400 EUV step and scan systems. Next year TSMC will start using EUV tools to pattern non-critical layers of chips made using its second-gen 7 nm fabrication technology (CLN7FF+). Usage of EUV for non-critical layers will bring a number of benefits to the CLN7FF+ vs. the original CLN7FF process, but the advantages will be limited: TSMC expects the CLN7FF+ to offer a 20% higher transistor density and a 10% lower power consumption at the same complexity and frequency when compared to the CLN7FF. TSMC's 5 nm (CLN5) technology will increase the usage of EUV tools and this will bring rather massive advantages when it comes to transistor density: TSMC is touting a 1.8x higher transistor density (~45% area reduction) when compared to the original CLN7FF, but it will only enable a 15% frequency gain (at the same complexity and power) or a 20% power reduction (at the same frequency and complexity). With the CLN5, TSMC will also offer an Extremely Low Threshold Voltage (ELTV) option that will enable its clients to increase frequencies of their chips by 25%, but the manufacturer has yet to describe the tech in greater detail.

1.8x higher transistor density and up to 15% frequency gain or 20% power reduction? You should be thankful you're getting anything!

Related: TSMC to Build 7nm Process Test Chips in Q1 2018
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020


Original Submission

Related Stories

TSMC to Build 7nm Process Test Chips in Q1 2018 4 comments

https://www.anandtech.com/show/11832/tsmc-teams-up-with-arm-and-cadence-to-build-7-nm-chip-in-q1-2018

TSMC has announced plans to build its first test chips for data center applications using its 7 nm fabrication technology. The chip will use compute cores from ARM, a Cache Coherent Interconnect for Accelerators (CCIX), and IP from Cadence (a DDR4 memory controller, PCIe 3.0/4.0 links). Given the presence of the CCIX bus and PCIe 4.0 interconnects, the chip will be used to show the benefits of TSMC's 7 nm process primarily for high-performance compute (HPC) applications. The IC will be taped out in early Q1 2018.

The 7 nm test chips from TSMC will be built mainly to demonstrate capabilities of the semiconductor manufacturing technology for performance-demanding applications and find out more about peculiarities of the process in general. The chip will be based on ARMv8.2 compute cores featuring DynamIQ, as well as a CMN-600 interconnect bus for heterogeneous multi-core CPUs. ARM and TSMC do not disclose which cores they are going to use for the device - the Cortex A55 and A75 are natural suspects, but that's speculation at this point. The new chip will also have a DDR4 memory controller as well as PCI Express 3.0/4.0 links, CCIX bus and peripheral IP buses developed by Cadence. The CCIX bus will be used to connect the chip to Xilinx's Virtex UltraScale+ FPGAs (made using a 16 nm manufacturing technology), so in addition to implementation of its cores using TSMC's 7 nm fabrication process, ARM will also be able to test Cadence's physical implementation of the CCIX bus for accelerators, which is important for future data center products.


Original Submission

TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020 3 comments

Taiwan Semiconductor Manufacturing Company (TSMC) plans to make so-called "5nm" chips starting in early 2020:

TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC's 5 nm process starting from early 2020. When all three phases of the manufacturing facility are completed, its wafer starts capacity will exceed one million 300-mm wafers per year, comparable with other three GigaFabs operated by TSMC.

TSMC's Fab 18 will be located in Tainan (in the Southern Taiwan Science Park), and will be built in three phases. The construction of the first phase or segment of the building will be completed in about a year from now, after which TSMC will move in equipment sometime in early 2019. In about two years from now, the company expects to start volume production of chips using its 5 nm process technology at the Fab 18/phase 1. Construction of the second and the third phases will commence in Q3 2018 and Q3 2019. The two phases will start volume production in 2020 and 2021, respectively.

Extreme ultraviolet (EUV) lithography could be used to make "7nm" chips, but not "5nm" yet.

Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm


Original Submission

Samsung Roadmap Includes "5nm", "4nm" and "3nm" Manufacturing Nodes 10 comments

Samsung has replaced planned "6nm" and "5nm" nodes with a new "5nm" node on its roadmap, and plans to continue scaling down to "3nm", which will use gate-all-around transistors instead of Fin Field-effect transistors. Extreme ultraviolet lithography (EUV) will be required for everything below "7nm" (TSMC and GlobalFoundries will start producing "7nm" chips without EUV initially):

Last year Samsung said that its 7LPP manufacturing technology will be followed up by 5LPP and 6LPP in 2019 (risk production). The new roadmap does not mention either processes, but introduces the 5LPE (5 nm low power early) that promises to "allow greater area scaling and ultra-low power benefits" when compared to 7LPP. It is unclear when Samsung plans to start using 5LPE for commercial products, but since it is set to replace 7LPP, expect the tech to be ready for risk production in 2019.

[...] Samsung will have two 4 nm process technologies instead of one — 4LPE and 4LPP. Both will be based on proven FinFETs and usage of this transistor structure is expected to allow timely ramp-up to the stable yield level. Meanwhile, the manufacturer claims that their 4 nm nodes will enable higher performance and geometry scaling when compared to the 5LPE, but is not elaborating beyond that (in fact, even the key differences between the three technologies are unclear). Furthermore, Samsung claims that 4LPE/4LPP will enable easy migration from 5LPE, but is not providing any details.

[...] The most advanced process technologies that Samsung announced this week are the 3GAAE/GAAP (3nm gate-all-around early/plus). Both will rely on Samsung's own GAAFET implementation that the company calls MBCFET (multi-bridge-channel FETs), but again, Samsung is not elaborating on any details. The only thing that it does say is that the MBCFET has been in development since 2002, so it will have taken the tech at least twenty years to get from an early concept to production.

MBCFETs are intended to enable Samsung to continue increasing transistor density while reducing power consumption and increasing the performance of its SoCs. Since the 3GAAE/GAAP technologies are three or four generations away, it is hard to make predictions about their actual benefits. What is safe to say is that the 3GAAE will be Samsung's fifth-generation EUV process technology and therefore will extensively use appropriate tools. Therefore, the success of the[sic] EUV in general will have a clear impact on Samsung's technologies several years down the road.

Previously: Samsung Plans a "4nm" Process

Related: IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process


Original Submission

GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack 15 comments

GlobalFoundries has halted development of its "7nm" low power node, will fire 5% of its staff, and will also halt most development of smaller nodes (such as "5nm" and "3nm"):

GlobalFoundries on Monday announced an important strategy shift. The contract maker of semiconductors decided to cease development of bleeding edge manufacturing technologies and stop all work on its 7LP (7 nm) fabrication processes, which will not be used for any client. Instead, the company will focus on specialized process technologies for clients in emerging high-growth markets. These technologies will initially be based on the company's 14LPP/12LP platform and will include RF, embedded memory, and low power features. Because of the strategy shift, GF will cut 5% of its staff as well as renegotiate its WSA and IP-related deals with AMD and IBM. In a bid to understand more what is going on, we sat down with Gary Patton, CTO of GlobalFoundries.

[...] Along with the cancellation of the 7LP, GlobalFoundries essentially canned all pathfinding and research operations for 5 nm and 3 nm nodes. The company will continue to work with the IBM Research Alliance (in Albany, NY) until the end of this year, but GlobalFoundries is not sure it makes sense to invest in R&D for 'bleeding edge' nodes given that it does not plan to use them any time soon. The manufacturer will continue to cooperate with IMEC, which works on a broader set of technologies that will be useful for GF's upcoming specialized fabrication processes, but obviously it will refocus its priorities there as well (more on GF's future process technologies later in this article).

So, the key takeaway here is that while the 7LP platform was a bit behind TSMC's CLN7FF when it comes to HVM – and GlobalFoundries has never been first to market with leading edge bulk manufacturing technologies anyway – there were no issues with the fabrication process itself. Rather there were deeper economic reasons behind the decision.

GlobalFoundries would have needed to use deep ultraviolet (DUV) instead of extreme ultraviolet (EUV) lithography for its initial "7nm" chips. It would have also required billions of dollars of investment to succeed on the "7nm" node, only to make less "7nm" chips than its competitors. The change in plans will require further renegotiation of GlobalFoundries' and AMD's Wafer Supply Agreement (WSA).

Meanwhile, AMD will move most of its business over to TSMC, although it may consider using Samsung:

TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April 13 comments

TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019

Last week, TSMC made two important announcements concerning its progress with extreme ultraviolet lithography (EUVL). First up, the company has successfully taped out its first customer chip using its second-generation 7 nm process technology, which incorporates limited EUVL usage. Secondly, TSMC disclosed plans to start risk production of 5 nm devices in April.

TSMC initiated high-volume manufacturing of chips using its first generation 7 nm fabrication process (CLN7FF, N7) in April. N7 is based around deep ultraviolet (DUV) lithography with ArF excimer lasers. By contrast, TSMC's second-generation 7 nm manufacturing technology (CLN7FF+, N7+) will use extreme ultraviolet lithography for four non-critical layers, mostly in a bid to speed up production and learn how to use ASML's Twinscan NXE step-and-scan systems for HVM. Factual information on the improvements from N7 to N7+ are rather limited: the new tech will offer a 20% higher transistor density (because of tighter metal pitch) and ~8% lower power consumption at the same complexity and frequency (between 6% and 12% to be more precise).

[...] After N7+ comes TSMC's first-generation 5 nm (CLN5FF, N5) process, which will use EUV on up to 14 layers. This will enable tangible improvements in terms of density, but will require TSMC to extensively use EUV equipment. When compared to TSMC's N7, N5 technology will enable TSMC's customers to shrink area of their designs by ~45% (i.e. transistor density of N5 is ~1.8x higher than that of N7), increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction[sic] (at the same frequency and complexity).

TSMC will be ready to start risk production of chips using its N5 tech in April, 2019. Keeping in mind that it typically takes foundries and their customers about a year to get from risk production to HVM, it seems like TSMC is on-track for mass production of 5 nm chips in Q2 2020, right in time to address smartphones due in the second half of 2020.

Tape-out. Risk production = early production.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process

Related: TSMC to Build 7nm Process Test Chips in Q1 2018
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Will Make AMD's "7nm" Epyc Server CPUs
GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack


Original Submission

ASML Plans to Ship 30 Extreme Ultraviolet Lithography (EUV) Scanners in 2019 13 comments

ASML to Ship 30 EUV Scanners in 2019: Faster EUV Tools Coming

ASML said last week that it planned to ship 30 extreme ultraviolet scanners in 2019, up significantly from 2018. The plan is not surprising, as demand for EUV lithography tools is rising and semiconductors manufacturers are building new fabs. In addition, ASML indicated plans to introduce a new EUV scanner that will offer a higher production throughput, the NXE: 3400C.

Last year ASML shipped (only) 18 Twinscan NXE: 3400B EUV scanners. This was slightly below its expectations, to supply 20 machines. In total, as of July 2018, there were 31 EUV scanners installed at various fabs across the world, including several machines in various semiconductor research organizations, including imec. If everything goes as planned, ASML will ship more extreme ultraviolet scanners in 2019 than it did in in years before that.

[...] Samsung Foundry has already started to use ASML's EUV equipment for production of commercial chips using its 7LPP process technology at its Fab S3.

[...] TSMC is set to start using its Twinscan NXE scanners for commercial wafers in the second half of this year to produce chips using its N7+ manufacturing technology. Initially EUV scanners will be used for non-critical layers, but their use will be expanded at the 5 nm node in 2020 – 2021.

[...] Demand for ASML's Twinscan NXE tools will be further boosted by demand from Intel and SK Hynix.

Previously: ASML Says Fire at Supplier Prodrive Will Lead to Delays Early Next Year

Related: TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process


Original Submission

TSMC's "5nm" (CLN5FF) Process On-Track for High-Volume Manufacturing in 2020 9 comments

TSMC's 5nm EUV Making Progress: Process design kits, design rule manual, electronic design automation tools, 3rd Party IP Ready

TSMC[*] this week said that it has completed development of tools required for design of SoCs that are made using its 5 nm (CLN5FF, N5) fabrication technology. The company indicated that some of its alpha customers (which use pre-production tools and custom designs) had already started risk production of their chips using its N5 manufacturing process, which essentially means that the technology is on-track for high-volume manufacturing (HVM) in 2020.

TSMC's N5 is the company's 2nd generation fabrication technology that uses both deep ultraviolet (DUV) as well as extreme ultraviolet (EUV) lithography. The process can use EUVL on up to 14 layers (a tangible progress from N7+, which uses EUVL on four non-critical layers) to enable significant improvements in terms of density. TSMC says that when compared to N7 (1st Gen 7 nm, DUV-only), N5 technology will allow chip developers to shrink die area of their designs by ~45%, making transistor density ~1.8x higher. It will also increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).

[*] TSMC - Taiwan Semiconductor Manufacturing Corporation

Same chip(let) size? Approximately double the core count.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April

Related: Samsung Plans to Make "5nm" Chips Starting in 2019-2020
ASML Plans to Ship 30 Extreme Ultraviolet Lithography (EUV) Scanners in 2019


Original Submission

Another Step Toward the End of Moore's Law 16 comments

At the end of March, two semiconductor manufacturing titans climbed another rung on the ladder of Moore's Law.

Taiwan Semiconductor (TSMC) announced 5nm manufacturing of at-risk-production while Samsung announced its own 5nm manufacturing process was ready for sampling.

TSMC says its 5-nm process offers a 15 percent speed gain or a 30 percent improvement in power efficiency. Samsung is promising a 10 percent performance improvement or a 20 percent efficiency improvement

Also, "both Samsung and TSMC are offering what they're calling a 6-nm process" as a kind of stepping stone for customers with earlier availability (H2 2019) vs 5nm production.

Unfortunately, but perhaps not unexpectedly, the playing field has narrowed significantly with the progression to 5nm foundry production

GlobalFoundries gave up at 14 nm and Intel, which is years late with its rollout of an equivalent to competitors' 7 nm, is thought to be pulling back on its foundry services, according to analysts.

Samsung and TSMC remain because they can afford the investment and expect a reasonable return. Samsung was the largest chipmaker by revenue in 2018, but its foundry business ranks fourth, with TSMC in the lead. TSMC's capital expenditure was $10 billion in 2018. Samsung expects to nearly match that on a per-year basis until 2030.

Can the industry function with only two companies capable of the most advanced manufacturing processes? "It's not a question of can it work?" says [G. Dan Hutcheson, at VLSI Research]. "It has to work."

According to Len Jelinek, a semiconductor-manufacturing analyst at IHS Markit. "As long as we have at least two viable solutions, then the industry will be comfortable"

There may only be two left, but neither company is sitting still:

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  • (Score: 2) by requerdanos on Sunday May 13 2018, @03:42PM (1 child)

    by requerdanos (5997) on Sunday May 13 2018, @03:42PM (#679208) Journal

    So despite impressive-sounding miniaturization gains, the performance-efficiency gains are not so impressive...

    1.8x higher transistor density and up to 15% frequency gain or 20% power reduction? You should be thankful you're getting anything!

    I don't know much about it, other than...

    • We are drawing ever-closer to the "as small as these things can go" because of how big the individual molecules are.
    • Engineering is hard.
    • There's no shortage of ignorant idiots declaring every few months "Today's CPU speeds are the best we will ever have."
    • Fortunately, neither is there a particular shortage of brilliant engineers.

    But I have a question for those who do. Is the apparent difference here likely because they were focusing on getting things smaller primarily, and in a future generation|iteration will be able to focus on getting things faster/more efficient? Or is it more likely that's about as good as this particular configuration will get, barring fine adjustments?

    • (Score: 4, Informative) by takyon on Sunday May 13 2018, @04:07PM

      by takyon (881) <{takyon} {at} {soylentnews.org}> on Sunday May 13 2018, @04:07PM (#679214) Journal

      the performance-efficiency gains are not so impressive...

      I disagree. I think the results are impressive. They just aren't "free lunch", "Ghost of Moore's Past" impressive. But not many things in life can just get a 10-20% improvement repeatedly, like semiconductor manufacturing can. The 1.8x density increase is a bigger deal and allows you to make more compact chips (for devices like smartwatches, smartglasses, phone/VR SoCs, whatever) or increase the number of cores, and as we know performance can sometimes scale up with the number of cores. If the number of CPU cores isn't increased, it can allow integrated graphics to be expanded again.

      Or is it more likely that's about as good as this particular configuration will get, barring fine adjustments?

      We still haven't switched to something more exotic like carbon nanotube transistors, or Silicon-Germanium, or tunnel field-effect transistors [wikipedia.org].

      Companies still see paths down to below 5nm or even 3nm:

      https://semiengineering.com/transistor-options-beyond-3nm/ [semiengineering.com]

      It’s even possible that today’s technology and its future iterations may provide enough performance beyond 5nm. Today’s leading-edge transistor type—the finFET—will likely extend to 5nm or 3nm, depending on how the nodes are defined. Then, at 4nm/3nm, some are moving toward a next-generation transistor technology called gate-all-around FETs, where a finFET is placed on its side and a gate is wrapped around it.

      [...] But there is also a chance the industry will require new and faster devices beyond gate-all-around. [...] So in R&D, the industry is working on several technologies for 2.5nm and 1.5nm. At those nodes, the industry could go down the following paths:

      • Extend gate-all-around FETs or develop more complex versions of the technology, such as complementary FETs (CFETs) and vertical nanowire FETs.
      • Take existing finFETs and tweak them with new materials, creating what’s called a negative-capacitance FET (NC-FET).
      • Integrate devices into an advanced package.

      Here's an article about gate-all-around transistors [soylentnews.org] from IBM.

      Part of the problem is that even if you can build at a tiny node, it isn't necessarily economical. Scaling has been slowed down, primarily to give more time for extreme ultraviolet lithography (EUV) to mature. At this point, it will probably gain traction at the 7nm node, with EUV used on only certain layers at first, and then the whole process later on.

      If traditional transistor types (to include stuff like gate-all-around), run out of steam, or we get as close to the atomic limits as possible, then we'll have a period of stagnation that will actually be good for everybody, because it will give us (big companies and startups) a chance to explore new approaches like the aforementioned nanotubes, etc. As long as it was possible to increase density and performance with slight adjustments, alternatives aren't fully and rapidly explored.

      One obvious path to more performance is to vertically stack transistors/cores. As long as your use case can tolerate an extreme emphasis on parallelism (such as graphics, multithreaded code, machine learning, etc.), then you can benefit from vertical stacking. Apparently, this may be coming soon with a technology referred to as "Wafer-on-Wafer" [soylentnews.org], which seems like a quick and dirty way to double performance.

      I will also submit the following story about Intel throwing money at a bunch of startups so that it doesn't become irrelevant: https://www.theregister.co.uk/2018/05/09/intel_moores_law_vc_investments/ [theregister.co.uk]

      --
      [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
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