The Taiwan Semiconductor Manufacturing Company (TSMC) has revealed a manufacturing technique (called wafer-on-wafer or WoW) that could allow CPUs and GPUs to take their first step towards vertical scaling:
Instead of one wafer per chip, future GPUs may include two or more wafers stacked vertically, which would double the performance without the need to develop new horizontal designs every 2 years. A dual wafer setup, for example, would be achieved by flipping the upper wafer over the lower one, binding both via a flip-chip package. Thus, future GPUs could include multiple wafers in one die and the operating system could detect it as a multi-processor graphics card, eliminating the need for SLI setups.
One shortcoming for this technology would be its lower manufacturing yields for sizes lower than 16 nm. If one of the stacked wafers does not pass the QA, the entire stack is discarded, leading to low yields and poor cost effectiveness. TSMC is currently working to improve this technology so that sub-12 nm processes could equally benefit from it.
Not discussed is how to deal with the heat generated in such a stack.
See also: Here's why Intel and AMD's 7nm CPU revolution is so important to the future of PCs
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Intel's Senior Vice President Jim Keller (who previously helped to design AMD's K8 and Zen microarchitectures) gave a talk at the Silicon 100 Summit that promised continued pursuit of transistor scaling gains, including a roughly 50x increase in gate density:
Intel's New Chip Wizard Has a Plan to Bring Back the Magic (archive)
In 2016, a biennial report that had long served as an industry-wide pledge to sustain Moore's law gave up and switched to other ways of defining progress. Analysts and media—even some semiconductor CEOs—have written Moore's law's obituary in countless ways. Keller doesn't agree. "The working title for this talk was 'Moore's law is not dead but if you think so you're stupid,'" he said Sunday. He asserted that Intel can keep it going and supply tech companies ever more computing power. His argument rests in part on redefining Moore's law.
[...] Keller also said that Intel would need to try other tactics, such as building vertically, layering transistors or chips on top of each other. He claimed this approach will keep power consumption down by shortening the distance between different parts of a chip. Keller said that using nanowires and stacking his team had mapped a path to packing transistors 50 times more densely than possible with Intel's 10 nanometer generation of technology. "That's basically already working," he said.
The ~50x gate density claim combines ~3x density from additional pitch scaling (from "10nm"), ~2x from nanowires, another ~2x from stacked nanowires, ~2x from wafer-to-wafer stacking, and ~2x from die-to-wafer stacking.
Related: Intel's "Tick-Tock" Strategy Stalls, 10nm Chips Delayed
Intel's "Tick-Tock" is Now More Like "Process-Architecture-Optimization"
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Another Step Toward the End of Moore's Law
TSMC Shows Colossal Interposer, Says Moore's Law Still Alive
In the company's first blog post, TSMC has stated that Moore's Law is still alive and well, despite the zeitgeist of recent times being the reverse. The company also showed a colossal 2500mm2 interposer that includes eight HBM memory chips and two big processors.
Godfrey Cheng, TSMC's new head of global marketing, wrote the blog post. He notes that Moore's Law is not about performance, but about transistor density. While performance traditionally improved by increasing the clock speed and architecture, today it is more often improved by increasing parallelization, and hence requires increases in chip size. This enhances the importance of transistor density because chip cost is directly proportional to its area.
[...] "one possible future of great density improvements is to allow the stacking of multiple layers of transistors in something we call Monolithic 3D Integrated Circuits. You could add a CPU on top of a GPU on top of an AI Edge engine with layers of memory in between. Moore's Law is not dead, there are many different paths to continue to increase density."
[...] [System-technology co-optimization (STCO)] is done through advanced packaging, for which TSMC supports silicon-based interposers and fan-out-based chiplet integration. It also has techniques to stack chips on wafers, or stack wafers on top of other wafers. As one such example, TSMC showed a nearly-2500mm2 silicon interposer – the world's largest – on top of which two 600mm2 processors are placed and eight 75mm2 HBM memory chips, which makes for 1800mm2 of compute and memory silicon on top of the interposer-based package, well over two times the conventional reticle size limit.
Related: Dual-Wafer Packaging (Wafer-on-Wafer) Could Double CPU/GPU Performance
Another Step Toward the End of Moore's Law
Intel's Jim Keller Promises That "Moore's Law" is Not Dead, Outlines 50x Improvement Plan
(Score: 0) by Anonymous Coward on Monday May 14 2018, @10:35PM
The return of the Pentium D.
(Score: 4, Interesting) by Snotnose on Monday May 14 2018, @10:53PM (4 children)
Some 10-15 years ago Qualcomm had a package that consisted of a FLASH chip sitting on top of the radio chip which sat on top of the baseband chip. SC2x or something.
I suspect the big problem here will be heat. When you have to put a big honkin heatsink on both your CPU and GPU whattaya gonna do, put a heat sink on both sides of the package? Run tubes for water cooling?
Why shouldn't we judge a book by it's cover? It's got the author, title, and a summary of what the book's about.
(Score: 2) by takyon on Monday May 14 2018, @11:05PM
Flash chips are a lot cooler, and 64-layer 3D NAND is available now.
Even a "2-layer" CPU or GPU would be a big change.
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(Score: 0) by Anonymous Coward on Tuesday May 15 2018, @01:30AM
https://www.youtube.com/watch?v=YpphKzmDiJM [youtube.com]
That may be a possible solution if it works as well as they are claiming in that video. QCOM got away with what they did at the time because it was a SoC for a phone that ran for 10+ days on 1 charge. Not exactly high voltage and max heat disp there. In the div I worked in we did not even bother with a heatsink on them.
(Score: 3, Insightful) by driverless on Tuesday May 15 2018, @01:30AM (1 child)
My immediate response as well, the title should be:
Stacking only works when you've got parts with relatively low heat output, e.g. a flash, older CPU, RAM stack. A CPU, CPU stack is just an expensive oven element.
(Score: 2) by TheRaven on Wednesday May 16 2018, @05:27AM
sudo mod me up
(Score: 2) by MichaelDavidCrawford on Monday May 14 2018, @11:44PM (3 children)
Every time I try it looks lovely ien a redirect loop
Yes I Have No Bananas. [gofundme.com]
(Score: 1, Informative) by Anonymous Coward on Monday May 14 2018, @11:55PM
A lot of websites are using redirect loops until javascript is running to keep spiders/crawlers from getting onto their website unless javascript is enabled.
Don't much appreciate it, but more and more sites seem to be using it.
(Score: 2) by takyon on Tuesday May 15 2018, @12:17AM (1 child)
Maybe it's Google One [techcrunch.com] deleting all of your files.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 0) by Anonymous Coward on Tuesday May 15 2018, @01:45AM
I doubt they are being deleted, the user is just losing access to them then they are being archived somehow. Do you have reason to think otherwise?
(Score: 2) by ese002 on Tuesday May 15 2018, @12:43AM (2 children)
Moore's law is driven by the expectation that wafer cost is more or less constant but newer processes allow more transistors to be packed on each wafer for "free".
If, instead of waiting for the process to double in density, you stack two wafers, you have doubled your manufacturing costs and that is before the yield hit is factored in. So cost is probably at least 3x for less than 2x performance and area.
The statement about not having to incur design costs are is bogus too. The interconnect has between the dies has to be designed too, along with the TSV's to reach the package pins. That's a significant cost in area and complexity so you probably won't do that for the first generation single-level chip. So, you need to design anew anyway.
So, what we have here is a technology for the most demanding consumers who want the highest performance available and are willing to pay for it. I don't see much application for the mainstream.
(Score: 2) by takyon on Tuesday May 15 2018, @03:47AM (1 child)
It's possible that two stacked wafers is somewhat cheaper than two wafers. Like how 64-layer NAND is not 64 times more expensive than 1/64 amount of planar NAND. In that case, there will be eager customers - probably not home users though.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by ese002 on Tuesday May 15 2018, @05:33PM
3D NAND is a monolith process. They don't fabricate 64 wafers and then stack them. They deposit 64 layers onto a single substrate (a relatively cheap operation) and then do a single exposure and etch through all 64 layers. It is really cool tech but only applicable to rigidly structured memory designs.
(Score: 2) by Runaway1956 on Tuesday May 15 2018, @01:11AM (4 children)
AMD has a long history of marketing chips that fail QA tests as a lower rated CPU. That is, a CPU that was intended to clock up to 3 Ghz has problems at 2.2 Ghz, is clocked down to 2 Ghz, and marketed as a 2 Ghz CPU. In such cases, AMD doesn't make the profit they would have wished, but they still recover their investment in that particular chip. Intel is less "transparent", but they market a variety of chips with various capabilities. It doesn't take any stretch of the imagination to envision their top performing chips passing every QA test, while those that don't quite make the cut are marketed as a lesser chip. The only restriction would be, architecture. You can't downgrade a chip to a class of chips with fewer pins, or entirely different voltages.
(Score: 2) by requerdanos on Tuesday May 15 2018, @01:53AM
...as easily.
Also, FTFS:
Should read: "Providing yet another form factor for" SLI setups. (Or crossfire setups, depending on which manufacturer's trademarks you're trading in.)
(Score: 2) by takyon on Tuesday May 15 2018, @03:49AM
Obviously, the way they bond these together is sensitive to defects. Maybe the defects even need to be mirrored for it to work.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 0) by Anonymous Coward on Tuesday May 15 2018, @11:38AM
In the SLI example given if one die dosen't work you just disable the non-working die. Simlar to how graphics cards currently are sold of lesser versions with less computing cores.
(Score: 2) by Grishnakh on Tuesday May 15 2018, @01:06PM
one of the stacked wafers does not pass the QA, the entire stack is discarded,
I don't get it. Why wouldn't they do some preliminary testing on the wafers before stacking them? Then they can discard one if it doesn't pass, or isn't good enough to be rated lower. They'll need to do further testing after stacking of course, since the stacking process could introduce a defect, but with modern automation, the cost of testing should be low.
(Score: 2) by black6host on Tuesday May 15 2018, @01:14AM (3 children)
Sure you have extra heat, so you double the output and decrease the life (I can't say by how much) of the chip. That's worst case scenario. And, to some, it might be worth the trade-off. Find a way to deal with the heat and then you got something cooking! :)
(Score: 1) by Kalas on Tuesday May 15 2018, @03:40AM (2 children)
Thanks for that mental image of someone frying an egg on their oversized heatsink.
(Score: 2) by black6host on Tuesday May 15 2018, @03:44AM
This is your brain on dual wafer chips...
(Score: 2) by Azuma Hazuki on Tuesday May 15 2018, @04:05AM
I could swear I saw a picture of someone doing that once (on a Prescott P4, natch).
I am "that girl" your mother warned you about...
(Score: 2, Funny) by Slartibartfast on Tuesday May 15 2018, @01:33AM
It sure is a good thing that *my* startup, producing flip-chipped vertically-stacked VCSEL arrays for a high-speed parallel fiber-optic transceiver didn't have ANY yield issues, because that might have left customers like Tyco and Cisco standing at the door, unable to buy transceivers in larger than test quantity, and preventing me from purchasing my own personal tropical island, sipping margaritas and certainly not typing some weird-ass sarcastic comment on Soylent News, or anything.
Oh. Wait.
(Score: 4, Funny) by Kalas on Tuesday May 15 2018, @03:37AM
So what you're saying is that we can expect some HOT wafer-on-wafer action in the near future?
Thanks, technology for catering to fetishes I didn't even know I had!