Rambus and Gigadrive Form Joint Venture to Commercialize Resistive RAM

Crossbar 3D Resistive RAM Heads to Commercialization 3 comments

In a Dec. 15 presentation at the 2014 International Electron Devices Meeting in San Francisco, Silicon Valley start-up Crossbar said that it has solved a major hurdle towards commercialization of its 3D/vertical resistive random-access memory (RRAM) product.

While 1TnR enables a single transistor to drive over 2,000 memory cells with very low power, it also experiences leakage of a sneak path current that interferes with the performance and reliability of a typical RRAM array. Crossbar's device solves that leakage problem by utilizing a super linear threshold layer. In that layer, a volatile conduction path is formed at the threshold voltage. This device is the industry's first selector capable of suppressing the leakage current at very small dimensions, and it has been successfully demonstrated in a four-megabit test memory chip.

Crossbar has previously made a number of bold claims about their potential NAND flash replacement: that it can fit 1 terabyte in an area the size of a postage stamp, while allowing 20x faster writes than NAND using 5% as much energy. Crossbar also claims 100,000 write cycles compared to NAND's 3,000-10,000. NAND endurance scaling issues have led Samsung, Hynix, SanDisk and Micron to pursue vertical-NAND in order to boost capacity and prolong endurance. Samsung has already commercialized V-NAND with the 850 EVO and 850 Pro SSD lines. Crossbar expects to produce RRAM for wearable devices starting in 2016, with RRAM-based SSDs appearing 18 months later.

In a related development also presented at IEDM, engineers at Stanford University have built a "four-layer prototype high-rise chip" using carbon nanotube transistors (CNTs) and RRAM. The researchers developed a new technique that transfers CNTs from a quartz growth medium to a silicon wafer using an adhesive metal film, "achieving some of the highest density, highest performance CNTs ever made." They fabricated RRAM layers directly atop each CNT logic layer while drilling thousands of interconnections between the layers.

Intel-Micron's 3D XPoint Memory Lacks Key Details 15 comments

Arthur T Knackerbracket has found some questions regarding a story we covered on Wednesday, in which Intel and Micron jointly announced their 3D XPoint memory. However, some are now asking how this can actually be used because the promised data rates far exceed anything with which current motherboards can cope. Some thoughts follow:

The 3D design uses a transistor-less cross point architecture to create a 3D design of interconnects, where memory cells sit at the intersection of word lines and bit lines, allowing the cells to be addressed individually. This means data can be read or written to and from the actual cells containing data and not the whole chip containing relevant cells.
Beyond that, though, we don't know much about the memory, like exactly what kind of memory it is. Is it phase change memory, ReRAM, MRAM or some other kind of memory? The two won't say. The biggest unanswered question in my mind is the bus for this new memory, which is supposed to start coming to market next year. The SATA III bus used by virtually all motherboards is already considered saturated. PCI Express is a faster alternative assuming you have the lanes for the data.
Making memory 1000 times faster isn't very useful if it chokes on the I/O bus, which is exactly what will happen if they use existing technology. It would be like a one-lane highway with no speed limit.
It needs a new use model. It can't be positioned as a hard drive alternative because the interfaces will choke it. So the question becomes what do they do? Clearly they need to come up with their own bus. Jim Handy, an analyst who follows the memory space, thinks it will be an SRAM interface. SRAM is used in CPU caches. This would mean the 3D XPoint memory would talk directly to the CPU.
"The beauty of an SRAM interface is that its really, really fast. What's not nice is it has a high pin count," he told me.
He also likes the implementation from Diablo Technologies, which basically built SSD drives in the shape of DDR3 memory sticks that plug into your motherboard memory slots. This lets the drives talk to the CPU at the speed of memory and not a hard drive.
One thing is for sure, the bus will be what makes or breaks 3D XPoint, because what good is a fast read if it chokes on the I/O interface?

Original Submission

IBM Demonstrates Phase Change Memory with Multiple Bits Per Cell 6 comments

takyon writes:

IBM researchers have created and tested phase change memory (PCM) that can store two bits per cell, and say that they see a path to three bits per cell, allowing for memory with a similar density to TLC NAND. IBM Research may be positioning PCM as a viable alternative to Intel and Micron's 3D XPoint, another "post-NAND" technology with DRAM-like speeds and write endurance, and NAND-like persistence, cost, and storage density:

"Phase change memory is the first instantiation of a universal memory with properties of both DRAM and flash, thus answering one of the grand challenges of our industry," Pozidis said with regard to the research that IBM has been doing. "Reaching three bits per cell is a significant milestone because at this density the cost of PCM will be significantly less than DRAM and closer to flash."
This is, of course, precisely the part of the memory hierarchy that Intel and Micron are pursuing with their 3D XPoint memory, which many speculate is based on resistive RAM (ReRAM) technologies, not PCM. At this time, 3D XPoint is implemented using a 20 nanometer process and stores data at a density of one bit per cell (SLC) and a 7 microsecond latency for reads and delivers on the order of 78,500 IOPS in a 70/30 read/write mix that is typically used to characterize storage. (These stats are courtesy of Chris Mellor over at our sister publication, The Register .) DRAM access is on the order of 200 nanoseconds, or about 35X faster than Intel's Optane 3D XPoint, but 3D XPoint is about four times faster on writes than a PCI-Express flash unit using the trimmed down NVM-Express protocol and about twelve times faster than this flash on reads.

Also at Tom's Hardware.

Multilevel-Cell Phase-Change Memory: A Viable Technology (DOI: 10.1109/JETCAS.2016.2528598)

Original Submission

HP/HPE's Memristor: Probably Dead 20 comments

takyon writes:

Don't count on memristor technology ever making it out of HPE Labs. It has been displaced by 3D XPoint and other competing memory/storage technologies:

Memristor was first reported by HPE Labs eight years ago, as a form of persistent memory. At the time HP Labs Fellow R. Stanley Williams compared it to flash: "It holds its memory longer. It's simpler. It's easier to make - which means it's cheaper - and it can be switched a lot faster, with less energy."
Unfortunately it isn't simpler to make and still isn't here. NVMe SSDs have boosted flash's data access speed, reducing the memory-storage gap, and Intel/Micron's 3D XPoint SSDs will arrive later this year as the first viable productised technology to fill that gap.
WDC's SanDisk unit is working on ReRAM technology for its entry into storage-class memory hardware, and HPE has a partnership with SanDisk over its use. SanDisk foundry partner Toshiba has a ReRAM interest. WDC's HGST unit has been involved with Phase Change Memory. IBM has demonstrated a 3bits/cell Phase Change Memory (PCM) technology. Samsung has no public storage-class memory initiative, although it has been involved in STT-RAM.
The problem for HPE with Memristor is that it would need volume manufacturing to get the cost down. Unless it can sell the potential chips to other server OEMs, it would be the only consumer of Memristor chips and have its servers compete with the XPoint-using OEMs that Intel and Micron are lining up.

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Western Digital and Samsung at the Flash Memory Summit 11 comments

takyon writes:

Western Digital has announced its intention to include 3D Resistive RAM (ReRAM) as storage class memory (SCM) in future SSDs and other products:

Without making any significant announcements this week, Western Digital indicated that it would use some of the things it has learnt while developing its BiCS 3D NAND to produce its ReRAM chips. The company claims that its ReRAM will feature a multi-layer cross-point implementation, something it originally revealed a while ago.
Perhaps, the most important announcement regarding the 3D ReRAM by Western Digital is the claim about scale and capital efficiency of the new memory. Essentially, this could mean that the company plans to use its manufacturing capacities as well as its infrastructure (testing, packaging, etc.) in Yokkaichi, Japan, to make 3D ReRAM. Remember that SCM is at this point more expensive than NAND, hence, it makes sense to continue using the current fabs and equipment to build both types of non-volatile memory so ensure that the SCM part of the business remains profitable.

One of WD's slides projects SCM as 50% the cost per gigabyte of DRAM in 2017, declining to 5% by 2023.

Samsung introduced its fourth generation of vertical NAND, with 64 layers:

With a per-die capacity of 512Gb (64GB), Samsung can now put 1TB of TLC flash in a single package. This means most product lines will be seeing an increase in capacity at the high end of the range. Their BGA SSD products will be offering 1TB capacity even in the 11.5mm by 13mm form factor. The 16TB PM1633a SAS SSD will be eclipsed by the new 32TB PM1643. Likely to be further out, the PM1725 PCIe add-in card SSD will be succeeded by the PM1735 with a PCIe 4 x8 host interface.
Complementing the NAND update will be a new non-standard oversized M.2 form factor 32mm wide and 114mm long, compared to the typical enterprise M.2 size of 22mm by 110mm. A little extra room can go a long way, and Samsung will be using it to produce 8TB drives. These will be enterprise SSDs and Samsung showed a diagram of these enabling 256TB of flash in a 1U server. Samsung will also be producing 4TB drives in standard M.2 sizing.
In what is likely a bid to steal some thunder from 3D XPoint memory before it can ship, Samsung announced Z-NAND memory technology and a Z-SSD product based around Z-NAND and a new SSD controller. They said nothing about the operating principles of Z-NAND, but they did talk about their plans for the Z-SSD products.

Original Submission

Fujitsu to Mass Produce Nantero-Licensed NRAM in 2018 25 comments

takyon writes:

A nanotube-based non-volatile RAM product could give Intel/Micron's 3D XPoint some competition:

Fujitsu announced that it has licensed Nantero's carbon nanotube-based NRAM (Non-volatile RAM) and will participate in a joint development effort to bring a 256Gb 55nm product to market in 2018. Carbon nanotubes are a promising technology projected to make an appearance in numerous applications, largely due to their incredible characteristics, which include unmatchable performance, durability and extreme temperature tolerance. Most view carbon nanotubes as a technology far off on the horizon, but Nantero has had working prototypes for several years.
[...] Other products also suffer limited endurance thresholds, whereas Nantero's NRAM has been tested up to 10^12 (1 trillion) cycles. The company stopped testing endurance at that point, so the upper bounds remain undefined. [...] The NRAM carbon nanotubes are 2nm in diameter. Much like NAND, fabs arrange the material into separate cells. NAND employs electrons to denote the binary value held in each cell (1 or 0), and the smallest lithographies hold roughly a dozen electrons per cell. NRAM employs several hundred carbon nanotubes per cell, and the tubes either attract or repel each other with the application of an electrical current, which signifies an "on" or "off" state. NRAM erases (resets) the cells with a phonon-driven technique that forces the nanotubes to vibrate and separate from each other. NRAM triggers the reset process by reversing the current, and it is reportedly more power efficient than competing memories (particularly at idle, where it requires no power at all).

NRAM could be much faster than 3D XPoint and suitable as universal memory for a concept like HP's "The Machine":

NRAM seems to be far faster than XPoint, and could be denser. An Intel Optane DIMM might have a latency of [7-9 µs] (7,000-9,000ns). Micron QuantX XPoint SSDs are expected to have latencies of [10 µs] for reading and [20 µs] for writing; that's 10,000 and 20,000ns respectively. A quick comparison has NRAM at c50ns or less and XPoint DIMMs at 7,000-10,000ns, 140-200 times slower. We might imagine that an XPoint/ReRAM-using server system has both DRAM and XPoint/ReRAM whereas an NRAM-using system might just use NRAM, once pricing facilitates this.

Another company licensing with Nantero is already looking to scale the NRAM down to 28nm.

Original Submission

Crossbar Searching for Funding and Customers for its ReRAM Products to Compete with Intel's Optane 3 comments

takyon writes:

Crossbar, which has talked up its version of a post-NAND memory/storage technology for years with little to show for it, now has to compete with the elephant in the room:

Crossbar, developer of Resistive RAM (ReRAM) chips, is setting up an AI consortium to help counter, er, resistance to the technology, speed up its adoption, and hopefully outrun Intel's Optane.
ReRAM is a type of non-volatile memory with DRAM-class access latency. So, flash-style solid-state storage with RAM-ish access. However, it is taking a long time to mature into a practical technology that can be deployed in devices to fill the gap between large-capacity, non-volatile, relatively slow NAND, and high-speed, relatively low capacity, volatile DRAM.
[...] Crossbar claims it can design "super dense 3D cross-point arrays, stackable with the capability to scale below 10nm, paving the way for terabytes on a single die." Beat that, Optane. Check out a white paper from the upstart here (registration needed.)
Crossbar continued to develop its ReRAM, inking a licensing agreement with Microsemi in May last year, involving the use of sub-10nm ReRAM tech in coming Microsemi products.
[...] Crossbar says it's working with Japanese authorities to review opportunities for the 2020 Olympics, including video-based event detection and response capability. We'll see if anything comes of that.

Previously: Crossbar 3D Resistive RAM Heads to Commercialization

Original Submission

Western Digital's Low Latency Flash: A Competitor to Intel's Optane (3D XPoint)? 2 comments

takyon writes:

Western Digital Develops Low-Latency Flash to Compete with Intel Optane

Western Digital is working on its own low-latency flash memory that will offer a higher performance and endurance when compared to conventional 3D NAND, ultimately designed to compete against Optane storage.
At Storage Field Day this week, Western Digital spoke about its new Low Latency Flash NAND. The technology is meant to fit somewhere between 3D NAND and DRAM, similar to Intel's Optane storage and Samsung's Z-NAND. Similar to those technologies, according to Western Digital, its LLF memory will feature access time "in the microsecond range", using 1 bit-per-cell and 2 bit-per-cell architectures.
[...] Western Digital does not disclose all the details regarding its low-latency flash memory and it is impossible to say whether it has anything to do with Toshiba's XL-Flash low-latency 3D NAND introduced last year as well as other specialized types of flash.
[...] In the more long term, Western Digital is working on ReRAM-based SCM internally, and on memristor-based SCM with HP.

The estimate is that WD's LLF memory will be 1/10th the cost of DRAM, and 3x as expensive as 3D NAND.

This sounds like a rebrand of SLC and MLC NAND.

Original Submission

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