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posted by chromas on Saturday July 28 2018, @01:28AM   Printer-friendly
from the epyc-story dept.

AMD "Rome" EPYC CPUs to Be Fabbed By TSMC

AMD CEO Lisa Su has announced that second-generation "Rome" EPYC CPU that the company is wrapping up work on is being produced out at TSMC. This is a notable departure from how things have gone for AMD with the Zen 1 generation, as GlobalFoundries has produced all of AMD's Zen CPUs, both for consumer Ryzen and professional EPYC parts.

[...] As it stands, AMD seems rather optimistic about how things are currently going. Rome silicon is already back in the labs, and indeed AMD is already sampling the parts to certain partners for early validation. Which means AMD remains on track to launch their second-generation EPYC processors in 2019.

[...] Ultimately however if they are meeting their order quota from GlobalFoundries, then AMD's situation is ultimately much more market driven: which fab can offer the necessary capacity and performance, and at the best prices. Which will be an important consideration as GlobalFoundries has indicated that it may not be able to keep up with 7nm demand, especially with the long manufacturing process their first-generation DUV-based 7nm "7LP" process requires.

See also: No 16-core AMD Ryzen AM4 Until After 7nm EPYC Launch (2019)

Related: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
Cray CS500 Supercomputers to Include AMD's Epyc as a Processor Option
AMD Returns to the Datacenter, Set to Launch "7nm" Radeon Instinct GPUs for Machine Learning in 2018
AMD Ratcheting Up the Pressure on Intel
More on AMD's Licensing of Epyc Server Chips to Chinese Companies


Original Submission

Related Stories

TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020 3 comments

Taiwan Semiconductor Manufacturing Company (TSMC) plans to make so-called "5nm" chips starting in early 2020:

TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC's 5 nm process starting from early 2020. When all three phases of the manufacturing facility are completed, its wafer starts capacity will exceed one million 300-mm wafers per year, comparable with other three GigaFabs operated by TSMC.

TSMC's Fab 18 will be located in Tainan (in the Southern Taiwan Science Park), and will be built in three phases. The construction of the first phase or segment of the building will be completed in about a year from now, after which TSMC will move in equipment sometime in early 2019. In about two years from now, the company expects to start volume production of chips using its 5 nm process technology at the Fab 18/phase 1. Construction of the second and the third phases will commence in Q3 2018 and Q3 2019. The two phases will start volume production in 2020 and 2021, respectively.

Extreme ultraviolet (EUV) lithography could be used to make "7nm" chips, but not "5nm" yet.

Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm


Original Submission

Cray CS500 Supercomputers to Include AMD's Epyc as a Processor Option 10 comments

Cray supercomputers with AMD Epyc processors will start shipping in the summer:

Cray is adding an AMD processor option to its CS500 line of clustered supercomputers.

The CS500 supports more than 11,000 nodes which can use Intel Xeon SP CPUs, optionally accelerated by Nvidia Tesla GPUs or Intel Phi co-processors. Intel Stratix FPGA acceleration is also supported.

There can be up to 72 nodes in a rack, interconnected by EDR/FDR InfiniBand or Intel's OmniPath fabric.

Cray has now added an AMD Epyc 7000 option to the CPU mix:

  • Systems provide four dual-socket nodes in a 2U chassis
  • Each node supports two PCIe 3.0 x 16 slots (200Gb network capability) and HDD/SSD options
  • Epyc 7000 processors support up to 32 cores and eight DDR4 memory channels per socket

Top-of-the-line Epyc chips have 32 cores and 64 threads. An upcoming generation of 7nm Epyc chips is rumored to have up to 48 or 64 cores, using 6 or 8 cores per Core Complex (CCX) instead of the current 4.

Related: AMD Epyc 7000-Series Launched With Up to 32 Cores
Intel's Skylake-SP vs AMD's Epyc
Data Centers Consider Intel's Rivals


Original Submission

AMD Returns to the Datacenter, Set to Launch "7nm" Radeon Instinct GPUs for Machine Learning in 2018 6 comments

AMD 7nm Vega Radeon Instinct GPU AI Accelerators Enter Lab Testing

AMD's current generation Vega graphics architecture – which powers its Radeon RX Vega family of graphics cards -- is based on a 14nm manufacturing process, but the chip company is already moving along with next generation process technology. During the company's conference call with analysts following its Q1 2018 earnings report (which it knocked out of the park, by the way), AMD CEO Dr. Lisa Su made some comments regarding its upcoming 7nm GPUs.

"I'm also happy to report that our next-generation 7-nanometer Radeon Instinct product, optimized for machine learning workloads, is running in our labs," said Dr. Su. "We remain on track to provide samples to customers later this year."

If you recall, Radeon Instinct is AMD's product line for machine intelligences and deep learning accelerators. The current lineup features a mixture of Polaris- and Vega-based GPUs and could be considered competitors for NVIDIA's Tesla family of products. [...] According to commentary from AMD at this year's CES, 7nm Vega products for mobile along with the 7nm Radeon Instinct accelerators will ship during the latter half of 2018.

From The Next Platform, "The Slow But Sure Return Of AMD In The Datacenter":

AMD Ratcheting Up the Pressure on Intel 24 comments

Intel expects to lose some server/data center market share to AMD's Epyc line of chips:

The pitched battle between Intel and AMD has spread to the data center, and while Intel has been forthcoming that it expects to lose some market share in the coming months to AMD, Brian Krzanich's recent comments to Instinet analyst Roman Shah give us some insight into the surprising scope of AMD's threat. Shah recently sat down with Intel CEO Brian Krzanich and Barron's reported on his findings:

Shah relates that Krzanich "was very matter-of-fact in saying that Intel would lose server share to AMD in the second half of the year," which is not news, but he thought it significant that "Mr. Krzanich did not draw a firm line in the sand as it relates to AMD's potential gains in servers; he only indicated that it was Intel's job to not let AMD capture 15-20% market share." (emphasis added).

Furthermore, Intel's problems with the "10nm" node could allow AMD to pick up market share with "7nm" (although it may be similar in performance to Intel's "10nm"):

Nomura Instinet is less bullish on further stock gains for Intel after talking to the chipmaker's CEO, Brian Krzanich. [...] The analyst said Intel's problems in moving to its next-generation chip manufacturing technology may be a factor in its potential market share losses. The chipmaker revealed on its April 26 earnings conference call that it delayed volume production under its 10-nanometer chip manufacturing process to next year. Conversely, AMD said on its call that it plans to start next-generation 7-nanometer chip production in late 2018.

[...] "We see Mr. Krzanich's posture here reflecting the company's inability thus far to sufficiently yield 10nm for volume production while AMD's partner TSMC is currently making good progress on 7nm; thus, setting Intel up for stiff competition again in 2019," the analyst said.

Here are a couple of post-mortem articles on Intel's misleading 28-core CPU demo and more:

Rather than 28 cores, Intel may introduce 20 and 22 core CPUs to compete with AMD's Threadripper 2, along with 8-core Coffee Lake refresh CPUs to compete with Ryzen.


Original Submission

More on AMD's Licensing of Epyc Server Chips to Chinese Companies 13 comments

Chinese companies are manufacturing chips nearly identical to AMD's Epyc server CPUs, using two joint ventures with AMD. This move comes after the US blacklisted certain Chinese supercomputing centers in 2015 in an attempt to prevent them from using Intel Xeon chips, and more recently, Chinese telecom equipment maker ZTE was banned from buying components from US companies. China's Sunway TaihuLight supercomputer (formerly #1 on the TOP500 list) also uses domestically designed Sunway SW26010 manycore chips.

AMD's Epyc "clone army" may end up hurting Intel's server chip market share even more than it already has:

China isn't eager to embrace another American chipmaker like AMD. In response, AMD established two joint ventures with Chinese holding company THATIC -- one with Chengdu Haiguang Microelectronics Technology (CHMT), and another with Haiguang IC Design, also known as Hygon.

AMD owns a majority stake in CHMT, which ensures that its IP isn't transferred to THATIC. THATIC owns a majority stake in Hygon, which licenses AMD's IP from CHMT. Hygon designs the chips, and CHMT produces the chips through a suitable foundry and then sends them back to Hygon for packaging, marketing, and sales.

This arrangement seemingly placates American and Chinese regulators -- AMD's IP isn't being passed to a Chinese company, and a Chinese chipmaker gains access to superior data center CPU designs. AMD generates less revenues through these JVs than it would through direct sales, but it still gains a foothold in China's massive data center market. But more importantly, this move could wound Intel.

Good luck maintaining control of your "IP". As for the pain?

Many big companies, including Microsoft and Baidu, started installing AMD's cheaper chips in their data centers. In a meeting with Nomura Instinet analyst Romit Shah in June, then-CEO Brian Krzanich admitted that AMD was gaining ground, and Intel was trying to prevent it from gaining a "15% to 20%" share of the data center market. That admission was stunning, since Intel traditionally controlled more than 99% of the data center market with its Xeon chips. Intel's data center group grew its revenues by 11% to $19.1 billion last year, and accounted for 30% of its top line. Epyc was already a thorn in Intel's side, but AMD's sponsorship of Chinese clones could throttle its sales in mainland China, which accounted for 24% of its sales last year. Its total sales in the region only rose 6% in 2017, compared to 20% growth in 2016.


Original Submission

GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack 15 comments

GlobalFoundries has halted development of its "7nm" low power node, will fire 5% of its staff, and will also halt most development of smaller nodes (such as "5nm" and "3nm"):

GlobalFoundries on Monday announced an important strategy shift. The contract maker of semiconductors decided to cease development of bleeding edge manufacturing technologies and stop all work on its 7LP (7 nm) fabrication processes, which will not be used for any client. Instead, the company will focus on specialized process technologies for clients in emerging high-growth markets. These technologies will initially be based on the company's 14LPP/12LP platform and will include RF, embedded memory, and low power features. Because of the strategy shift, GF will cut 5% of its staff as well as renegotiate its WSA and IP-related deals with AMD and IBM. In a bid to understand more what is going on, we sat down with Gary Patton, CTO of GlobalFoundries.

[...] Along with the cancellation of the 7LP, GlobalFoundries essentially canned all pathfinding and research operations for 5 nm and 3 nm nodes. The company will continue to work with the IBM Research Alliance (in Albany, NY) until the end of this year, but GlobalFoundries is not sure it makes sense to invest in R&D for 'bleeding edge' nodes given that it does not plan to use them any time soon. The manufacturer will continue to cooperate with IMEC, which works on a broader set of technologies that will be useful for GF's upcoming specialized fabrication processes, but obviously it will refocus its priorities there as well (more on GF's future process technologies later in this article).

So, the key takeaway here is that while the 7LP platform was a bit behind TSMC's CLN7FF when it comes to HVM – and GlobalFoundries has never been first to market with leading edge bulk manufacturing technologies anyway – there were no issues with the fabrication process itself. Rather there were deeper economic reasons behind the decision.

GlobalFoundries would have needed to use deep ultraviolet (DUV) instead of extreme ultraviolet (EUV) lithography for its initial "7nm" chips. It would have also required billions of dollars of investment to succeed on the "7nm" node, only to make less "7nm" chips than its competitors. The change in plans will require further renegotiation of GlobalFoundries' and AMD's Wafer Supply Agreement (WSA).

Meanwhile, AMD will move most of its business over to TSMC, although it may consider using Samsung:

TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April 13 comments

TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019

Last week, TSMC made two important announcements concerning its progress with extreme ultraviolet lithography (EUVL). First up, the company has successfully taped out its first customer chip using its second-generation 7 nm process technology, which incorporates limited EUVL usage. Secondly, TSMC disclosed plans to start risk production of 5 nm devices in April.

TSMC initiated high-volume manufacturing of chips using its first generation 7 nm fabrication process (CLN7FF, N7) in April. N7 is based around deep ultraviolet (DUV) lithography with ArF excimer lasers. By contrast, TSMC's second-generation 7 nm manufacturing technology (CLN7FF+, N7+) will use extreme ultraviolet lithography for four non-critical layers, mostly in a bid to speed up production and learn how to use ASML's Twinscan NXE step-and-scan systems for HVM. Factual information on the improvements from N7 to N7+ are rather limited: the new tech will offer a 20% higher transistor density (because of tighter metal pitch) and ~8% lower power consumption at the same complexity and frequency (between 6% and 12% to be more precise).

[...] After N7+ comes TSMC's first-generation 5 nm (CLN5FF, N5) process, which will use EUV on up to 14 layers. This will enable tangible improvements in terms of density, but will require TSMC to extensively use EUV equipment. When compared to TSMC's N7, N5 technology will enable TSMC's customers to shrink area of their designs by ~45% (i.e. transistor density of N5 is ~1.8x higher than that of N7), increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction[sic] (at the same frequency and complexity).

TSMC will be ready to start risk production of chips using its N5 tech in April, 2019. Keeping in mind that it typically takes foundries and their customers about a year to get from risk production to HVM, it seems like TSMC is on-track for mass production of 5 nm chips in Q2 2020, right in time to address smartphones due in the second half of 2020.

Tape-out. Risk production = early production.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process

Related: TSMC to Build 7nm Process Test Chips in Q1 2018
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Will Make AMD's "7nm" Epyc Server CPUs
GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack


Original Submission

Oracle Offers Servers with AMD's Epyc to its Cloud Customers 1 comment

Oracle puts AMD EPYC in the Cloud

The process of AMD ramping up its EPYC efforts involves a lot of 'first-step' vendor interaction. Having been a very minor player for so long, all the big guns are taking it slowly with AMD's newest hardware in verifying whether it is suitable for their workloads and customers. The next company to tick that box is Oracle, who is announcing today that they will be putting bare metal EPYC instances available in its cloud offering.

The new E-series instances will start with Standard E2, costing around $0.03 per core per hour, up to 64 cores per server, Oracle is stating that this pricing structure is 66% less than the average per-core instance on the market. One bare metal standard instance, BM.Standard E2.52, will offer dual EPYC 7551 processors at 2.0 GHz, with 512 GB of DDR4, dual 25GbE networking, and up to 1PB of remote block storage. Another offering is the E2.64 instance, which will offer 16 cores by comparison.

Related: AMD Epyc 7000-Series Launched With Up to 32 Cores
Data Centers Consider Intel's Rivals
Cray CS500 Supercomputers to Include AMD's Epyc as a Processor Option
AMD Returns to the Datacenter, Set to Launch "7nm" Radeon Instinct GPUs for Machine Learning in 2018
Chinese Company Produces Chips Closely Based on AMD's Zen Microarchitecture
More on AMD's Licensing of Epyc Server Chips to Chinese Companies
TSMC Will Make AMD's "7nm" Epyc Server CPUs


Original Submission

Intel Announces 48-core Xeons Using Multiple Dies, Ahead of AMD Announcement 23 comments

Intel announces Cascade Lake Xeons: 48 cores and 12-channel memory per socket

Intel has announced the next family of Xeon processors that it plans to ship in the first half of next year. The new parts represent a substantial upgrade over current Xeon chips, with up to 48 cores and 12 DDR4 memory channels per socket, supporting up to two sockets.

These processors will likely be the top-end Cascade Lake processors; Intel is labelling them "Cascade Lake Advanced Performance," with a higher level of performance than the Xeon Scalable Processors (SP) below them. The current Xeon SP chips use a monolithic die, with up to 28 cores and 56 threads. Cascade Lake AP will instead be a multi-chip processor with multiple dies contained with in a single package. AMD is using a similar approach for its comparable products; the Epyc processors use four dies in each package, with each die having 8 cores.

The switch to a multi-chip design is likely driven by necessity: as the dies become bigger and bigger it becomes more and more likely that they'll contain a defect. Using several smaller dies helps avoid these defects. Because Intel's 10nm manufacturing process isn't yet good enough for mass market production, the new Xeons will continue to use a version of the company's 14nm process. Intel hasn't yet revealed what the topology within each package will be, so the exact distribution of those cores and memory channels between chips is as yet unknown. The enormous number of memory channels will demand an enormous socket, currently believed to be a 5903 pin connector.

Intel also announced tinier 4-6 core E-2100 Xeons with ECC memory support.

Meanwhile, AMD is holding a New Horizon event on Nov. 6, where it is expected to announce 64-core Epyc processors.

Related: AMD Epyc 7000-Series Launched With Up to 32 Cores
AVX-512: A "Hidden Gem"?
Intel's Skylake-SP vs AMD's Epyc
Intel Teases 28 Core Chip, AMD Announces Threadripper 2 With Up to 32 Cores
TSMC Will Make AMD's "7nm" Epyc Server CPUs
Intel Announces 9th Generation Desktop Processors, Including a Mainstream 8-Core CPU


Original Submission

AMD Previews Zen 2 Epyc CPUs with up to 64 Cores, New "Chiplet" Design 9 comments

AMD has announced the next generation of its Epyc server processors, with up to 64 cores (128 threads) each. Instead of an 8-core "core complex" (CCX), AMD's 64-core chips will feature 8 "chiplets" with 8 cores each:

AMD on Tuesday formally announced its next-generation EPYC processor code-named Rome. The new server CPU will feature up to 64 cores featuring the Zen 2 microarchitecture, thus providing at least two times higher performance per socket than existing EPYC chips.

As discussed in a separate story covering AMD's new 'chiplet' design approach, AMD EPYC 'Rome' processor will carry multiple CPU chiplets manufactured using TSMC's 7 nm fabrication process as well as an I/O die produced at a 14 nm node. As it appears, high-performance 'Rome' processors will use eight CPU chiplets offering 64 x86 cores in total.

Why chiplets?

Separating CPU chiplets from the I/O die has its advantages because it enables AMD to make the CPU chiplets smaller as physical interfaces (such as DRAM and Infinity Fabric) do not scale that well with shrinks of process technology. Therefore, instead of making CPU chiplets bigger and more expensive to manufacture, AMD decided to incorporate DRAM and some other I/O into a separate chip. Besides lower costs, the added benefit that AMD is going to enjoy with its 7 nm chiplets is ability to easier[sic] bin new chips for needed clocks and power, which is something that is hard to estimate in case of servers.

AMD also announced that Zen 4 is under development. It could be made on a "5nm" node, although that is speculation. The Zen 3 microarchitecture will be made on TSMC's N7+ process ("7nm" with more extensive use of extreme ultraviolet lithography).

AMD's Epyc CPUs will now be offered on Amazon Web Services.

AnandTech live blog of New Horizon event.

Previously: AMD Epyc 7000-Series Launched With Up to 32 Cores
TSMC Will Make AMD's "7nm" Epyc Server CPUs
Intel Announces 48-core Xeons Using Multiple Dies, Ahead of AMD Announcement

Related: Cray CS500 Supercomputers to Include AMD's Epyc as a Processor Option
Oracle Offers Servers with AMD's Epyc to its Cloud Customers


Original Submission

AMD Improves Server Market Share by 100%... to 2% 11 comments

AMD's EPYC CPUs have already snatched server market share away from Intel

Intel has enjoyed a virtual monopoly in the server CPU arena for some time. However, AMD's EPYC series of processors, based on the latest iteration of Zen architecture, may change that. The first generation of these chipsets, Naples, managed to reduce Intel's market share to 99% shortly after its launch. This may sound less than impressive, but in a billion-dollar industry, it was possibly quite valuable to AMD.

The latest report on the server market by DRAMeXchange indicates that Intel's share is down to 98% by now. This represents a 100% improvement for AMD. Furthermore, the analysts estimate that the release of EPYC Rome-based silicon will result in further gains. They will ultimately result in a total market share of 5% for these CPUs by the end of 2019.

Intel is keeping AMD under 15%. For now:

Now it's easy to tell that Intel will still remain the dominant player in the market, retaining a 90-95% market share lead over AMD but Intel's Ex-CEO, Brian Krzanich, stated that his company wouldn't want AMD capturing 15-20% server market share. In fact, at the pace at which AMD is gaining their server market share, 15% doesn't really feel like a far cry from now.

[...] Looking at the market penetration rate, Intel's Purley platform has been adopted by 60% users in the server space and is expected to reach 65% in the coming year. On the other hand, AMD's EPYC Naples platform has been adopted by 70% and considering that AMD is keeping socket longevity intact with Rome, we can see the adoption rate further expanding after 7nm chips launch.

Previously: AMD Misses Q1 Earnings Target; Withdraws from High-Density Server Market
AMD Ratcheting Up the Pressure on Intel
More on AMD's Licensing of Epyc Server Chips to Chinese Companies
AMD's server marketshare hits 1% for the first time in 4 years

Related: TSMC Will Make AMD's "7nm" Epyc Server CPUs
Intel Announces 48-core Xeons Using Multiple Dies, Ahead of AMD Announcement


Original Submission

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  • (Score: 3, Interesting) by bzipitidoo on Saturday July 28 2018, @04:50AM (1 child)

    by bzipitidoo (4388) Subscriber Badge on Saturday July 28 2018, @04:50AM (#713930) Journal

    I try to get more years out of my computers than a mere 5, but such rapid and large upgrades make it hard to justify keeping old boxes plugged in. Plus, hard drives these days have about a 5 year life span. I'm still getting a little use out of decade old 45nm and 65nm stuff, and (assuming marketing hasn't perverted die size measurements to make them worthless) here we are with 14nm and talking of 10nm and 7nm, and in another few years, 5nm. 5nm is such a gigantic upgrade from 14nm, I suppose in 2 years they too won't be worth the electricity it takes to run them.

    • (Score: 2) by takyon on Saturday July 28 2018, @05:43AM

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Saturday July 28 2018, @05:43AM (#713935) Journal

      It's useful for as long as you find it useful.

      If the stuff you are typically doing doesn't feel sluggish, then you don't need more speed. If the machine is idling most of the time and not under load, then you don't need the greater power efficiency.

      Keep the hard drive contents backed up frequently. Swap in an SSD when it dies.

      --
      [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
  • (Score: 2) by takyon on Saturday July 28 2018, @06:49AM (1 child)

    by takyon (881) <takyonNO@SPAMsoylentnews.org> on Saturday July 28 2018, @06:49AM (#713945) Journal

    Seen this in the past couple of days?

    https://www.top500.org/news/leaked-intel-roadmap-reveals-some-surprises-for-hpc-customers/ [top500.org]

    No boost in core count for Cascade Lake-SP. AMD could drop 64 core server chips onto Intel's measly 28 cores.

    But there is Cascade Lake-AP at the bottom. Maybe an attempt at making Xeon Phi into the flagship product?

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    [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
    • (Score: 2) by opinionated_science on Saturday July 28 2018, @12:21PM

      by opinionated_science (4031) on Saturday July 28 2018, @12:21PM (#713974)

      that lack of AVX512 on AMD is a sticking point. Some calculations benefit considerably from the density.

      Plus, I suspect some twiddling could turn the AVX machinery into "Machine Learning" units...

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