GlobalFoundries has halted development of its "7nm" low power node, will fire 5% of its staff, and will also halt most development of smaller nodes (such as "5nm" and "3nm"):
GlobalFoundries on Monday announced an important strategy shift. The contract maker of semiconductors decided to cease development of bleeding edge manufacturing technologies and stop all work on its 7LP (7 nm) fabrication processes, which will not be used for any client. Instead, the company will focus on specialized process technologies for clients in emerging high-growth markets. These technologies will initially be based on the company's 14LPP/12LP platform and will include RF, embedded memory, and low power features. Because of the strategy shift, GF will cut 5% of its staff as well as renegotiate its WSA and IP-related deals with AMD and IBM. In a bid to understand more what is going on, we sat down with Gary Patton, CTO of GlobalFoundries.
[...] Along with the cancellation of the 7LP, GlobalFoundries essentially canned all pathfinding and research operations for 5 nm and 3 nm nodes. The company will continue to work with the IBM Research Alliance (in Albany, NY) until the end of this year, but GlobalFoundries is not sure it makes sense to invest in R&D for 'bleeding edge' nodes given that it does not plan to use them any time soon. The manufacturer will continue to cooperate with IMEC, which works on a broader set of technologies that will be useful for GF's upcoming specialized fabrication processes, but obviously it will refocus its priorities there as well (more on GF's future process technologies later in this article).
So, the key takeaway here is that while the 7LP platform was a bit behind TSMC's CLN7FF when it comes to HVM – and GlobalFoundries has never been first to market with leading edge bulk manufacturing technologies anyway – there were no issues with the fabrication process itself. Rather there were deeper economic reasons behind the decision.
GlobalFoundries would have needed to use deep ultraviolet (DUV) instead of extreme ultraviolet (EUV) lithography for its initial "7nm" chips. It would have also required billions of dollars of investment to succeed on the "7nm" node, only to make less "7nm" chips than its competitors. The change in plans will require further renegotiation of GlobalFoundries' and AMD's Wafer Supply Agreement (WSA).
Meanwhile, AMD will move most of its business over to TSMC, although it may consider using Samsung:
In short, AMD is now shifting over the bulk of their bleeding-edge development to TSMC. The company is careful to note that they "intend to focus the breadth" of their 7nm production at TSMC rather than all 7nm production – leaving open the possibility of using TSMC rival Samsung in the future – but the message is clear that we should expect AMD's major 7nm products to be fabbed out of TSMC now that GlobalFoundries is no longer an option.
TSMC being AMD's new bleeding-edge partner should of course come as no surprise, as TSMC has been the fab AMD has fallen back on for other projects in the past. TSMC was until the most recent generation the fab AMD used for their GPUs, and it's where their semi-custom APUs for Microsoft and Sony have been made. Meanwhile AMD and TSMC have already previously announced that some of AMD's forthcoming 7nm products, including their 7nm Vega and "Rome" EPYC CPU would be fabbed by the Taiwanese foundry. So today's announcement is largely confirmation that AMD is going to continue down this path, with most (if not all) of their other planned 7nm products ending up at TSMC as well.
NO NO NO: AMD, GlobalFoundries Renew Vows, Focus on Path to 7nm (NO)
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm (NO NO)
AnandTech Interview With the CTO of GlobalFoundries: 7nm EUV and 5 GHz Clock Speeds (NO NO NO)
Related: TSMC to Build 7nm Process Test Chips in Q1 2018
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
Samsung Roadmap Includes "5nm", "4nm" and "3nm" Manufacturing Nodes
AMD Ratcheting Up the Pressure on Intel
Samsung Plans to Make "5nm" Chips Starting in 2019-2020
TSMC Will Make AMD's "7nm" Epyc Server CPUs
Related Stories
AMD and its primary fab partner GlobalFoundries have signed an updated five-year wafer supply agreement that will extend through the end of 2020. The restructuring simultaneously deepens the commitment between the partners and gives AMD limited freedom to see other foundries. In exchange, GlobalFoundries will get some additional compensation.
Per the terms of the agreement, which pertains to AMD's microprocessor, graphics processor, and semi-custom products, AMD will make $25 million cash installments to GlobalFoundries over the next four quarters, for a total cash transfer of $100 million. Beginning in 2017, AMD will be required to make quarterly payments to GlobalFoundries based on the volume of certain wafers it is obtaining from another foundry.
The agreement also stipulates annual wafer purchase targets for the five-year period, sets fixed wafer prices for 2016, and provides a framework for yearly wafer pricing. If annual targets are not met, a penalty will be imposed based on the difference between actual wafer purchases and the target for that year.
takyon: Those are some of the costs of outsourcing your semiconductor fabrication. Let's hope AMD meets those targets.
TSMC has announced plans to build its first test chips for data center applications using its 7 nm fabrication technology. The chip will use compute cores from ARM, a Cache Coherent Interconnect for Accelerators (CCIX), and IP from Cadence (a DDR4 memory controller, PCIe 3.0/4.0 links). Given the presence of the CCIX bus and PCIe 4.0 interconnects, the chip will be used to show the benefits of TSMC's 7 nm process primarily for high-performance compute (HPC) applications. The IC will be taped out in early Q1 2018.
The 7 nm test chips from TSMC will be built mainly to demonstrate capabilities of the semiconductor manufacturing technology for performance-demanding applications and find out more about peculiarities of the process in general. The chip will be based on ARMv8.2 compute cores featuring DynamIQ, as well as a CMN-600 interconnect bus for heterogeneous multi-core CPUs. ARM and TSMC do not disclose which cores they are going to use for the device - the Cortex A55 and A75 are natural suspects, but that's speculation at this point. The new chip will also have a DDR4 memory controller as well as PCI Express 3.0/4.0 links, CCIX bus and peripheral IP buses developed by Cadence. The CCIX bus will be used to connect the chip to Xilinx's Virtex UltraScale+ FPGAs (made using a 16 nm manufacturing technology), so in addition to implementation of its cores using TSMC's 7 nm fabrication process, ARM will also be able to test Cadence's physical implementation of the CCIX bus for accelerators, which is important for future data center products.
GlobalFoundries: Next-generation chip factories will cost at least $10 billion
The economics of the chip industry are pretty staggering. Sanjay Jha, CEO of contract chip manufacturer Globalfoundries, recently told me that it could cost between $10 billion and $12 billion to build a next-generation chip factory based on the latest technology, dubbed 7-nanometer production. And one for the generation after that, dubbed 5-nanometer production, could cost $14 billion to $18 billion.
There are only a few companies in the world that can afford to spend that much money on a chip factory. And they can do it because those chips are expected to generate billions of dollars in revenue over the life of the factory.
Dean Takahashi from VentureBeat interviewed Sanjay Jha, CEO of GlobalFoundries:
Basically, the numbers don't mean much these days. I think Samsung has talked about 10nm, 11nm, 14nm, 8nm, 7nm, 6nm. I don't know what they mean. The way to think about 12nm is it has higher performance and more scale than 14nm. It's not quite the scaling or performance of 10nm. Performance may be very close to 10nm, though.
Taiwan Semiconductor Manufacturing Company (TSMC) plans to make so-called "5nm" chips starting in early 2020:
TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC's 5 nm process starting from early 2020. When all three phases of the manufacturing facility are completed, its wafer starts capacity will exceed one million 300-mm wafers per year, comparable with other three GigaFabs operated by TSMC.
TSMC's Fab 18 will be located in Tainan (in the Southern Taiwan Science Park), and will be built in three phases. The construction of the first phase or segment of the building will be completed in about a year from now, after which TSMC will move in equipment sometime in early 2019. In about two years from now, the company expects to start volume production of chips using its 5 nm process technology at the Fab 18/phase 1. Construction of the second and the third phases will commence in Q3 2018 and Q3 2019. The two phases will start volume production in 2020 and 2021, respectively.
Extreme ultraviolet (EUV) lithography could be used to make "7nm" chips, but not "5nm" yet.
Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
AnandTech's Ian Cutress interviewed Dr. Gary Patton, CTO of GlobalFoundries. A number of topics were discussed, including the eventual use of ASML's extreme ultraviolet lithography (EUV) for the "7nm" node:
Q13: With EUV still in the process of being brought up, and the way it is with counting masks and pellicle support coming through, is there ever a mentality of 7nm not getting EUV, and that 7nm could end up a purely optical transition? Do you fully expect EUV to come in at 7nm?
GP: I absolutely believe that EUV is here. It's coming, I absolutely believe it so. As you've seen with the machines we are installing in the clean room, we have placed a big bet on it. As Tom (Thomas Caulfield) was saying, it's a pretty high scale investment. I think if you look at the tool itself, for example, ASML has demonstrated 250W with it. This is pretty repeatable, so I think that it looks in good shape. There are some challenges with the collector availability. They are getting close, I think around 75% availability now is pretty solid, but they have to get to 85%, and they are cranking these tools out. Even with this as a work in progress, there are going to be a lot of tools out on the field, and that is going to also help with improving the performance and control of the tools. The tools we have here are the ultimate tools, the ultimate manufacturing versions.
The lithographic resist is a little bit of a challenge, but we are still trying to optimize that. I don't see that as a show stopper, as we are managing throughout bring up. I think the real challenge is the masks, and I feel very good about the pellicle process. They have made a lot of progress, and they have shown it can handle 250W. The biggest issue has been that you lose a bit of power - so you've done all this work to get to 250W, and then you just lost 20% of that. So it has to go up another 10%, so it's closer to 90%, in terms of a loss to be viable. For contacts and vias, we can run without pellicles. We have the right inspection infrastructure to manage that, and then bring the pellicles in when they are ready.
[...] Q17: Does the first generation of 7LP target higher frequency clocks than 14LPP?
GP: Definitely. It is a big performance boost - we quoted around 40%. I don't know how that exactly will translate into frequency, but I would guess that it should be able to get up in the 5GHz range, I would expect.
Imec and Cadence Tape Out Industry's First 3nm Test Chip
The world-leading research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. today announced that its extensive, long-standing collaboration has resulted in the industry's first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.
A tape-out is the final step before the design is sent to be fabricated.
Meanwhile, Imec is looking towards nodes smaller than "3nm":
[...] industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, according to the International Technology Roadmap for Semiconductors (ITRS) version 2.0. Another organization, Imec, is more aggressive with the timetable, saying that 2.5nm or thereabouts will arrive by 2024.
Also at EE Times.
Related: TSMC Plans New Fab for 3nm
Samsung Plans a "4nm" Process
IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details 5 nm Process Tech: Aggressive Scaling, But Thin Power and Performance Gains
At a special event last week, TSMC announced the first details about its 5 nm manufacturing technology that it plans to use sometime in 2020. CLN5 will be the company's second fabrication process to use extreme ultraviolet (EUV) lithography, which is going to enable TSMC to aggressively increase its transistor density versus prior generations. However, when it comes to performance and power improvements, the gains do not look very significant.
Just like other fabs, TSMC will gradually ramp up usage of ASML's Twinscan NXE:3400 EUV step and scan systems. Next year TSMC will start using EUV tools to pattern non-critical layers of chips made using its second-gen 7 nm fabrication technology (CLN7FF+). Usage of EUV for non-critical layers will bring a number of benefits to the CLN7FF+ vs. the original CLN7FF process, but the advantages will be limited: TSMC expects the CLN7FF+ to offer a 20% higher transistor density and a 10% lower power consumption at the same complexity and frequency when compared to the CLN7FF. TSMC's 5 nm (CLN5) technology will increase the usage of EUV tools and this will bring rather massive advantages when it comes to transistor density: TSMC is touting a 1.8x higher transistor density (~45% area reduction) when compared to the original CLN7FF, but it will only enable a 15% frequency gain (at the same complexity and power) or a 20% power reduction (at the same frequency and complexity). With the CLN5, TSMC will also offer an Extremely Low Threshold Voltage (ELTV) option that will enable its clients to increase frequencies of their chips by 25%, but the manufacturer has yet to describe the tech in greater detail.
1.8x higher transistor density and up to 15% frequency gain or 20% power reduction? You should be thankful you're getting anything!
Related: TSMC to Build 7nm Process Test Chips in Q1 2018
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
Samsung has replaced planned "6nm" and "5nm" nodes with a new "5nm" node on its roadmap, and plans to continue scaling down to "3nm", which will use gate-all-around transistors instead of Fin Field-effect transistors. Extreme ultraviolet lithography (EUV) will be required for everything below "7nm" (TSMC and GlobalFoundries will start producing "7nm" chips without EUV initially):
Last year Samsung said that its 7LPP manufacturing technology will be followed up by 5LPP and 6LPP in 2019 (risk production). The new roadmap does not mention either processes, but introduces the 5LPE (5 nm low power early) that promises to "allow greater area scaling and ultra-low power benefits" when compared to 7LPP. It is unclear when Samsung plans to start using 5LPE for commercial products, but since it is set to replace 7LPP, expect the tech to be ready for risk production in 2019.
[...] Samsung will have two 4 nm process technologies instead of one — 4LPE and 4LPP. Both will be based on proven FinFETs and usage of this transistor structure is expected to allow timely ramp-up to the stable yield level. Meanwhile, the manufacturer claims that their 4 nm nodes will enable higher performance and geometry scaling when compared to the 5LPE, but is not elaborating beyond that (in fact, even the key differences between the three technologies are unclear). Furthermore, Samsung claims that 4LPE/4LPP will enable easy migration from 5LPE, but is not providing any details.
[...] The most advanced process technologies that Samsung announced this week are the 3GAAE/GAAP (3nm gate-all-around early/plus). Both will rely on Samsung's own GAAFET implementation that the company calls MBCFET (multi-bridge-channel FETs), but again, Samsung is not elaborating on any details. The only thing that it does say is that the MBCFET has been in development since 2002, so it will have taken the tech at least twenty years to get from an early concept to production.
MBCFETs are intended to enable Samsung to continue increasing transistor density while reducing power consumption and increasing the performance of its SoCs. Since the 3GAAE/GAAP technologies are three or four generations away, it is hard to make predictions about their actual benefits. What is safe to say is that the 3GAAE will be Samsung's fifth-generation EUV process technology and therefore will extensively use appropriate tools. Therefore, the success of the[sic] EUV in general will have a clear impact on Samsung's technologies several years down the road.
Previously: Samsung Plans a "4nm" Process
Related: IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
Intel expects to lose some server/data center market share to AMD's Epyc line of chips:
The pitched battle between Intel and AMD has spread to the data center, and while Intel has been forthcoming that it expects to lose some market share in the coming months to AMD, Brian Krzanich's recent comments to Instinet analyst Roman Shah give us some insight into the surprising scope of AMD's threat. Shah recently sat down with Intel CEO Brian Krzanich and Barron's reported on his findings:
Shah relates that Krzanich "was very matter-of-fact in saying that Intel would lose server share to AMD in the second half of the year," which is not news, but he thought it significant that "Mr. Krzanich did not draw a firm line in the sand as it relates to AMD's potential gains in servers; he only indicated that it was Intel's job to not let AMD capture 15-20% market share." (emphasis added).
Furthermore, Intel's problems with the "10nm" node could allow AMD to pick up market share with "7nm" (although it may be similar in performance to Intel's "10nm"):
Nomura Instinet is less bullish on further stock gains for Intel after talking to the chipmaker's CEO, Brian Krzanich. [...] The analyst said Intel's problems in moving to its next-generation chip manufacturing technology may be a factor in its potential market share losses. The chipmaker revealed on its April 26 earnings conference call that it delayed volume production under its 10-nanometer chip manufacturing process to next year. Conversely, AMD said on its call that it plans to start next-generation 7-nanometer chip production in late 2018.
[...] "We see Mr. Krzanich's posture here reflecting the company's inability thus far to sufficiently yield 10nm for volume production while AMD's partner TSMC is currently making good progress on 7nm; thus, setting Intel up for stiff competition again in 2019," the analyst said.
Here are a couple of post-mortem articles on Intel's misleading 28-core CPU demo and more:
Rather than 28 cores, Intel may introduce 20 and 22 core CPUs to compete with AMD's Threadripper 2, along with 8-core Coffee Lake refresh CPUs to compete with Ryzen.
Samsung is preparing to manufacture 7LPP and 5LPE process ARM chips:
Samsung has said its chip foundry building Arm Cortex-A76-based processors will use 7nm process tech in the second half of the year, with 5nm product expected mid-2019 using the extreme ultra violet (EUV) lithography process.
The A76 64-bit chips will be able to pass 3GHz in clock speed. Back in May we wrote: "Arm reckoned a 3GHz 7nm A76 single core is up to 35 per cent faster than a 2.8GHz 10nm Cortex-A75, as found in Qualcomm's Snapdragon 845, when running mixed integer and floating-point math benchmarks albeit in a simulator."
[...] Samsung eventually envisages moving to a 3nm Gate-All-Round-Early (3AAE) on its process technology roadmap. Catch up, Intel, if you can.
Also at AnandTech.
Previously: Samsung Roadmap Includes "5nm", "4nm" and "3nm" Manufacturing Nodes
Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap (obsolete)
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process
AMD "Rome" EPYC CPUs to Be Fabbed By TSMC
AMD CEO Lisa Su has announced that second-generation "Rome" EPYC CPU that the company is wrapping up work on is being produced out at TSMC. This is a notable departure from how things have gone for AMD with the Zen 1 generation, as GlobalFoundries has produced all of AMD's Zen CPUs, both for consumer Ryzen and professional EPYC parts.
[...] As it stands, AMD seems rather optimistic about how things are currently going. Rome silicon is already back in the labs, and indeed AMD is already sampling the parts to certain partners for early validation. Which means AMD remains on track to launch their second-generation EPYC processors in 2019.
[...] Ultimately however if they are meeting their order quota from GlobalFoundries, then AMD's situation is ultimately much more market driven: which fab can offer the necessary capacity and performance, and at the best prices. Which will be an important consideration as GlobalFoundries has indicated that it may not be able to keep up with 7nm demand, especially with the long manufacturing process their first-generation DUV-based 7nm "7LP" process requires.
See also: No 16-core AMD Ryzen AM4 Until After 7nm EPYC Launch (2019)
Related: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
Cray CS500 Supercomputers to Include AMD's Epyc as a Processor Option
AMD Returns to the Datacenter, Set to Launch "7nm" Radeon Instinct GPUs for Machine Learning in 2018
AMD Ratcheting Up the Pressure on Intel
More on AMD's Licensing of Epyc Server Chips to Chinese Companies
Samsung Foundry Updates: 8LPU Added, EUVL on Track for HVM in 2019
Samsung recently hosted its Samsung Foundry Forum 2018 in Japan, where it made several significant foundry announcements. Besides reiterating plans to start high-volume manufacturing (HVM) using extreme ultraviolet lithography (EUVL) tools in the coming quarters, along with reaffirming plans to use gate all around FETs (GAAFETs) with its 3 nm node, the company also added its brand-new 8LPU process technology to its roadmap. Samsung Foundry's general roadmap was announced earlier this year, so at SFF in Japan the contract maker of semiconductors reiterated some of its plans, made certain corrections, and provided some additional details about its future plans.
TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019
Last week, TSMC made two important announcements concerning its progress with extreme ultraviolet lithography (EUVL). First up, the company has successfully taped out its first customer chip using its second-generation 7 nm process technology, which incorporates limited EUVL usage. Secondly, TSMC disclosed plans to start risk production of 5 nm devices in April.
TSMC initiated high-volume manufacturing of chips using its first generation 7 nm fabrication process (CLN7FF, N7) in April. N7 is based around deep ultraviolet (DUV) lithography with ArF excimer lasers. By contrast, TSMC's second-generation 7 nm manufacturing technology (CLN7FF+, N7+) will use extreme ultraviolet lithography for four non-critical layers, mostly in a bid to speed up production and learn how to use ASML's Twinscan NXE step-and-scan systems for HVM. Factual information on the improvements from N7 to N7+ are rather limited: the new tech will offer a 20% higher transistor density (because of tighter metal pitch) and ~8% lower power consumption at the same complexity and frequency (between 6% and 12% to be more precise).
[...] After N7+ comes TSMC's first-generation 5 nm (CLN5FF, N5) process, which will use EUV on up to 14 layers. This will enable tangible improvements in terms of density, but will require TSMC to extensively use EUV equipment. When compared to TSMC's N7, N5 technology will enable TSMC's customers to shrink area of their designs by ~45% (i.e. transistor density of N5 is ~1.8x higher than that of N7), increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction[sic] (at the same frequency and complexity).
TSMC will be ready to start risk production of chips using its N5 tech in April, 2019. Keeping in mind that it typically takes foundries and their customers about a year to get from risk production to HVM, it seems like TSMC is on-track for mass production of 5 nm chips in Q2 2020, right in time to address smartphones due in the second half of 2020.
Tape-out. Risk production = early production.
Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
Related: TSMC to Build 7nm Process Test Chips in Q1 2018
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Will Make AMD's "7nm" Epyc Server CPUs
GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack
GlobalFoundries Establishes Avera Semiconductor: a Custom Chip Company
GlobalFoundries this week announced that it has spun off its ASIC Solutions division, establishing Avera Semiconductor, a wholly owned subsidiary that will help fabless chip developers to design their products. Avera will work closely with GlobalFoundries' customers to enable them take advantage of various process technologies that GF has, but the company will also establish ties with other contract makers of semiconductors to help their clients develop chips to be made using leading edge process technologies at 7 nm and beyond.
[...] The new wholly owned subsidiary of GlobalFoundries has over 850 employees, an annual revenue of over $500 million, and ongoing projects worth $3 billion. By working not only with clients of GlobalFoundries, but expanding to customers of companies like Samsung Foundry and TSMC, Avera has a chance to increase its earnings over time. Avera Semi is led by Kevin O'Buckley, a former head of ASIC Solutions, who joined GlobalFoundries from IBM.
Shuffling money on the Titanic?
Previously: AMD, GlobalFoundries Renew Vows, Focus on Path to 7nm
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
AnandTech Interview With the CTO of GlobalFoundries: 7nm EUV and 5 GHz Clock Speeds
GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack
Related: Can Intel Really Share its Fabs?
GlobalFoundries Files Patent Claims Against TSMC, Seeks to Ban Imports of Nvidia, Apple Chips
GlobalFoundries (GF) today announced that it filed lawsuits against Taiwan Semiconductor Manufacturing Company (TSMC) in the U.S. and Germany over the alleged infringement of 16 patents. The company said that it's looking to halt the import of processors made with the technologies and is seeking "significant damages from TSMC based on TSMC's unlawful use of GF's proprietary technology in its tens of billions of dollars of sales." Impacted companies include Nvidia and Apple.
Note that GlobalFoundries said it wants to stop the import of processors made with the technologies it believes are covered by its patents. The company recognized that TSMC doesn't usually import those processors into the U.S. or Germany; TSMC's customers do. That means the lawsuits could affect much of the tech industry: TSMC said that in 2018 it was "manufacturing 10,436 different products using 261 distinct technologies for 481 different customers."
The list of companies supplied by TSMC includes AMD, Nvidia, Apple, Mediatek and many others, which means that GlobalFoundries could bring the tech industry to a halt if it's allowed to stop imports to the U.S. and Germany.
If you can't beat 'em, sue 'em.
Also at Wccftech.
Related: GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack
GlobalFoundries Spins Off ASIC Solutions Division, Creating a New Subsidiary: Avera Semiconductor
Imec Develops Efficient Processor In Memory Technique for GloFo
Imec and GlobalFoundries have demonstrated a processor-in-memory chip that can achieve energy efficiency up to 2900 TOPS/W, approximately two orders of magnitude above today's commercial processor-in-memory chips. The chip uses an established idea, analog computing, implemented in SRAM in GlobalFoundries' 22nm fully-depleted silicon-on-insulator (FD-SOI) process technology. Imec's analog in-memory compute (AiMC) will be available to GlobalFoundries customers as a feature that can be implemented on the company's 22FDX platform.
Since a neural network model may have tens or hundreds of millions of weights, sending data back and forth between the memory and the processor is inefficient. Analog computing uses a memory array to store the weights and also perform multiply-accumulate (MAC) operations, so there is no memory-to-processor transfer needed. Each memristor element (perhaps a ReRAM cell) has its conductance programmed to an analog level which is proportional to the required weight.
[...] Imec has built a test chip, called analog inference accelerator (AnIA), based on GlobalFoundries' 22nm FD-SOI process. AnIA's 512k array of SRAM cells plus digital infrastructure including 1024 DACs and 512 ADCs takes up 4mm2. It can perform around half a million computations per operation cycle based on 6-bit (plus sign bit) input activations, ternary weights (-1, 0, +1) and 6-bit outputs.
[...] Imec showed accuracy results for object recognition inference on the CIFAR 10 dataset which dropped only one percentage point compared to a similarly quantised baseline. With a supply voltage of 0.8 V, AnIA's energy efficiency is between 1050 and 1500 TOPS/W at 23.5 TOPS. For 0.6 V supply voltage, AnIA achieved 5.8 TOPS at around 1800-2900 TOPS/W.
Promising application: edge computing facial recognition cameras for the surveillance state.
Also at Wccftech.
See also: Week In Review: Auto, Security, Pervasive Computing
Previously: IBM Reduces Neural Network Energy Consumption Using Analog Memory and Non-Von Neumann Architecture
Related: "3nm" Test Chip Taped Out by Imec and Cadence
GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack - "The manufacturer will continue to cooperate with IMEC, which works on a broader set of technologies that will be useful for GF's upcoming specialized fabrication processes..."
Radar for Your Wrist
(Score: 0) by Anonymous Coward on Tuesday August 28 2018, @03:02PM (2 children)
Some sales rep and sales manager just saw their biggest clients go to TSMC, which means kissing their sales commissions goodbye.
It may make a lot of financial sense for GF to stop burning cash in the R&D wars. These days, as soon as one fab technology is in production its successor (and its successor's successor) is already under development. That doesn't leave a lot of time to squeeze an ROI from the initial R&D costs (which are staggering in this industry). I guess cutting $20 - $30bn in future expenses means losing all the cutting edge client sales may turn out to be more profitable.
(Score: 4, Informative) by takyon on Tuesday August 28 2018, @03:20PM
I can imagine that GlobalFoundries gets out of the fab race, only to license a smaller node than "7nm" when it needs to. It's unclear how many new nodes there will be, but "5nm" and "3nm" are likely. The first "7nm" chips won't even use EUV, so they will be pretty expensive to produce. Untold billions will be spent on fabrication at these smaller nodes. TSMC will spend it, and Samsung will definitely spend it since they are making a killing off of memory and NAND.
GlobalFoundries could be better off ceding business to TSMC and Samsung for now. GloFo will come back later on some ridiculous node such as "3nm". Around that point, there will be few improvements left to make without radical changes such as quantum-exploiting transistors (e.g. TFETs), new materials, and 3D/stacked/layered chips, any of which will require additional $billions to develop.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by JoeMerchant on Tuesday August 28 2018, @03:50PM
He's part of the 5% (well, probably not counted in the 5%, but part of the RIF strategy anyway.)
🌻🌻 [google.com]
(Score: 2) by DannyB on Tuesday August 28 2018, @03:33PM (7 children)
Surely they know their business, their customers, etc. Maybe they don't have enough customer prospects for 7nm to see any profit in a reasonable time frame. So stick with what they've got, and existing contracts, and do it well at a good price.
Does that seem to capture the short version of what this is about?
The people who rely on government handouts and refuse to work should be kicked out of congress.
(Score: 2) by JoeMerchant on Tuesday August 28 2018, @03:58PM (3 children)
There was one hell of a big issue with the 7LP fabrication process itself: the cost to make it work. If they could have done it cheaply enough, they would have stayed with it and maybe even licensed their tech out to other foundries. They gauged the landscape, saw this wasn't going to be profitable for them, saw that they have large continuing markets for their 10 and 14nm processes, and figured that those buggy whips are good enough to keep flogging them for years to come.
When the old foundries can no longer operate profitably because all the customer money is going to the higher tech / lower power chips, then they'll switch over. Personally, I'm disappointed in the current generation of Intel NUCs because they're bumping up the power draws - I'd really like to see them going in the other direction, but that's not what the market is driving right now, maybe it's time for AMD to remind Intel that power consumption matters again, like they did around 2006.
Or, maybe someday, the ARM devices that power things like the RPi will finally get up to speed and give a "normal" computing experience. They've dramatically improved over the years, and I'd consider them "useable" as a graphic desktop for many tasks, but they're still not quite there as a total replacement for something like a NUC, whereas a NUC is a pretty good replacement for anything that isn't more or less trying to use a lot of compute resources.
🌻🌻 [google.com]
(Score: 2) by takyon on Tuesday August 28 2018, @04:03PM (2 children)
*12 and 14nm. "12nm" is a slightly improved version of the "14nm" process. They were going to skip "10nm" and go straight to "7nm". Now they are skipping it all.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by JoeMerchant on Tuesday August 28 2018, @08:29PM (1 child)
Crap sells - it's as easy as that, why develop something new and better when you can make money off of the existing formula?
This is all too true where I work, also.
🌻🌻 [google.com]
(Score: 3, Interesting) by takyon on Tuesday August 28 2018, @08:55PM
Older, mature nodes still get used years after they cease to be state-of-the-art.
https://en.wikipedia.org/wiki/65-nanometer_process [wikipedia.org]
Nikon Expeed 2 – 2010
MCST Elbrus 4C – 2014
SRISA 1890VM9Ya – 2016
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(Score: 4, Interesting) by takyon on Tuesday August 28 2018, @03:58PM (1 child)
It might not encompass the enormous impact of this decision. They are abandoning all development of smaller nodes. That doesn't mean they can't come back at a later date after skipping a couple of nodes, but they have left the race, perhaps for good (and for the good of the company). You're not going to be buying many more AMD/Nvidia products made by GlobalFoundries.
I can't really criticize this decision. TSMC and Samsung might end up looking like the suckers if they continue to blow $10-20 billion on new fabs. EUV has been delayed for years. 450mm wafers are dead in the water, maybe forever [eetimes.com].
https://en.wikipedia.org/wiki/Moore%27s_second_law [wikipedia.org]
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(Score: 2) by DannyB on Tuesday August 28 2018, @04:27PM
Interesting, and more comprehensible. Thanks.
The people who rely on government handouts and refuse to work should be kicked out of congress.
(Score: 2, Informative) by Anonymous Coward on Tuesday August 28 2018, @04:41PM
Competing with TSMC is tough. They currently control 56% of foundry market share:
https://www.semiwiki.com/forum/content/7693-globalfoundries-pivoting-away-bleeding-edge-technologies.html [semiwiki.com]
I imagine Samsung can stay in the race because of their internal product demand and knowledge sharing with their memory division. Intel's difficulties migrating to their 10nm (eff 7nm) node is well known, and with Intel moving to a new CEO the future of their foundry work is uncertain at best.
It will be interesting to see what happens to GF's 7nm process tools. EUV scanners are the biggest visibility, and also literally the biggest financially and physically. They already have their 14nm node yielding so printing with EUV in 14nm is overkill. If their financiers are trying to turn a profit those tools will probably get sold, but otherwise keeping those tools for experiments could be useful. Other process tools are less expensive and probably easier to stomach keeping on-site for an older process node.
I could see GF leveraging their 7nm learnings for making some very unique custom products. Particularly military and automotive applications have tough requirements: military needs USA made chips with high reliability and sometimes radiation hardening. Automotive components have safety regulations that can be stricter than healthcare tools and are rated for crazy environments (years of use ranging from Arizona heat to Florida humidity and salt to Alaska winters, while being exposed to the engine bay's heat cycling).
(Score: 3, Informative) by RamiK on Tuesday August 28 2018, @03:54PM (2 children)
https://www.extremetech.com/computing/276169-amd-moves-all-7nm-cpu-gpu-production-to-tsmc [extremetech.com]
NASDAQ: NVDA is hilarious :D
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(Score: 2) by takyon on Tuesday August 28 2018, @04:09PM (1 child)
So it won't be delayed to 2019? Nice.
AMD needs to bullshit up some cores that can do real-time raytracing. They probably aren't too far behind Nvidia since it was an inevitable development, Microsoft announced that raytracing API back in March, and there's been years of research preceding this. I guess we'll see if AMD tries to take on Nvidia with machine learning capabilities on the GPU (which can now be used for raytracing noise removal).
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 3, Interesting) by RamiK on Tuesday August 28 2018, @05:35PM
Meh. Just give me more polygons, decent video decode and FOSS it all up and I'm happy :D
Btw, 4th edition Real-Time Rendering just came out including Chakravarty's work on noise reduction so there might be alternative solutions referenced there that AMD might have developed/taken if you're feeling curious.
compiling...
(Score: 0) by Anonymous Coward on Tuesday August 28 2018, @05:06PM
"Meanwhile, AMD will move most of its business over to TSMC, although it may consider using Samsung:"
maybe now AMD will be able to put chips on the shelves when needed.