Slash Boxes

SoylentNews is people

posted by martyb on Wednesday October 10 2018, @09:16PM   Printer-friendly
from the wherefore-art-thou-Intel? dept.

TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019

Last week, TSMC made two important announcements concerning its progress with extreme ultraviolet lithography (EUVL). First up, the company has successfully taped out its first customer chip using its second-generation 7 nm process technology, which incorporates limited EUVL usage. Secondly, TSMC disclosed plans to start risk production of 5 nm devices in April.

TSMC initiated high-volume manufacturing of chips using its first generation 7 nm fabrication process (CLN7FF, N7) in April. N7 is based around deep ultraviolet (DUV) lithography with ArF excimer lasers. By contrast, TSMC's second-generation 7 nm manufacturing technology (CLN7FF+, N7+) will use extreme ultraviolet lithography for four non-critical layers, mostly in a bid to speed up production and learn how to use ASML's Twinscan NXE step-and-scan systems for HVM. Factual information on the improvements from N7 to N7+ are rather limited: the new tech will offer a 20% higher transistor density (because of tighter metal pitch) and ~8% lower power consumption at the same complexity and frequency (between 6% and 12% to be more precise).

[...] After N7+ comes TSMC's first-generation 5 nm (CLN5FF, N5) process, which will use EUV on up to 14 layers. This will enable tangible improvements in terms of density, but will require TSMC to extensively use EUV equipment. When compared to TSMC's N7, N5 technology will enable TSMC's customers to shrink area of their designs by ~45% (i.e. transistor density of N5 is ~1.8x higher than that of N7), increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction[sic] (at the same frequency and complexity).

TSMC will be ready to start risk production of chips using its N5 tech in April, 2019. Keeping in mind that it typically takes foundries and their customers about a year to get from risk production to HVM, it seems like TSMC is on-track for mass production of 5 nm chips in Q2 2020, right in time to address smartphones due in the second half of 2020.

Tape-out. Risk production = early production.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process

Related: TSMC to Build 7nm Process Test Chips in Q1 2018
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Will Make AMD's "7nm" Epyc Server CPUs
GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack

Original Submission

Related Stories

TSMC to Build 7nm Process Test Chips in Q1 2018 4 comments

TSMC has announced plans to build its first test chips for data center applications using its 7 nm fabrication technology. The chip will use compute cores from ARM, a Cache Coherent Interconnect for Accelerators (CCIX), and IP from Cadence (a DDR4 memory controller, PCIe 3.0/4.0 links). Given the presence of the CCIX bus and PCIe 4.0 interconnects, the chip will be used to show the benefits of TSMC's 7 nm process primarily for high-performance compute (HPC) applications. The IC will be taped out in early Q1 2018.

The 7 nm test chips from TSMC will be built mainly to demonstrate capabilities of the semiconductor manufacturing technology for performance-demanding applications and find out more about peculiarities of the process in general. The chip will be based on ARMv8.2 compute cores featuring DynamIQ, as well as a CMN-600 interconnect bus for heterogeneous multi-core CPUs. ARM and TSMC do not disclose which cores they are going to use for the device - the Cortex A55 and A75 are natural suspects, but that's speculation at this point. The new chip will also have a DDR4 memory controller as well as PCI Express 3.0/4.0 links, CCIX bus and peripheral IP buses developed by Cadence. The CCIX bus will be used to connect the chip to Xilinx's Virtex UltraScale+ FPGAs (made using a 16 nm manufacturing technology), so in addition to implementation of its cores using TSMC's 7 nm fabrication process, ARM will also be able to test Cadence's physical implementation of the CCIX bus for accelerators, which is important for future data center products.

Original Submission

TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020 3 comments

Taiwan Semiconductor Manufacturing Company (TSMC) plans to make so-called "5nm" chips starting in early 2020:

TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC's 5 nm process starting from early 2020. When all three phases of the manufacturing facility are completed, its wafer starts capacity will exceed one million 300-mm wafers per year, comparable with other three GigaFabs operated by TSMC.

TSMC's Fab 18 will be located in Tainan (in the Southern Taiwan Science Park), and will be built in three phases. The construction of the first phase or segment of the building will be completed in about a year from now, after which TSMC will move in equipment sometime in early 2019. In about two years from now, the company expects to start volume production of chips using its 5 nm process technology at the Fab 18/phase 1. Construction of the second and the third phases will commence in Q3 2018 and Q3 2019. The two phases will start volume production in 2020 and 2021, respectively.

Extreme ultraviolet (EUV) lithography could be used to make "7nm" chips, but not "5nm" yet.

Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm

Original Submission

"3nm" Test Chip Taped Out by Imec and Cadence 13 comments

Imec and Cadence Tape Out Industry's First 3nm Test Chip

The world-leading research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. today announced that its extensive, long-standing collaboration has resulted in the industry's first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.

A tape-out is the final step before the design is sent to be fabricated.

Meanwhile, Imec is looking towards nodes smaller than "3nm":

[...] industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, according to the International Technology Roadmap for Semiconductors (ITRS) version 2.0. Another organization, Imec, is more aggressive with the timetable, saying that 2.5nm or thereabouts will arrive by 2024.

Also at EE Times.

Related: TSMC Plans New Fab for 3nm
Samsung Plans a "4nm" Process
IBM Demonstrates 5nm Chip With Horizontal Gate-All-Around Transistors
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020

Original Submission

TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process 2 comments

TSMC Details 5 nm Process Tech: Aggressive Scaling, But Thin Power and Performance Gains

At a special event last week, TSMC announced the first details about its 5 nm manufacturing technology that it plans to use sometime in 2020. CLN5 will be the company's second fabrication process to use extreme ultraviolet (EUV) lithography, which is going to enable TSMC to aggressively increase its transistor density versus prior generations. However, when it comes to performance and power improvements, the gains do not look very significant.

Just like other fabs, TSMC will gradually ramp up usage of ASML's Twinscan NXE:3400 EUV step and scan systems. Next year TSMC will start using EUV tools to pattern non-critical layers of chips made using its second-gen 7 nm fabrication technology (CLN7FF+). Usage of EUV for non-critical layers will bring a number of benefits to the CLN7FF+ vs. the original CLN7FF process, but the advantages will be limited: TSMC expects the CLN7FF+ to offer a 20% higher transistor density and a 10% lower power consumption at the same complexity and frequency when compared to the CLN7FF. TSMC's 5 nm (CLN5) technology will increase the usage of EUV tools and this will bring rather massive advantages when it comes to transistor density: TSMC is touting a 1.8x higher transistor density (~45% area reduction) when compared to the original CLN7FF, but it will only enable a 15% frequency gain (at the same complexity and power) or a 20% power reduction (at the same frequency and complexity). With the CLN5, TSMC will also offer an Extremely Low Threshold Voltage (ELTV) option that will enable its clients to increase frequencies of their chips by 25%, but the manufacturer has yet to describe the tech in greater detail.

1.8x higher transistor density and up to 15% frequency gain or 20% power reduction? You should be thankful you're getting anything!

Related: TSMC to Build 7nm Process Test Chips in Q1 2018
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020

Original Submission

TSMC Will Make AMD's "7nm" Epyc Server CPUs 4 comments

AMD "Rome" EPYC CPUs to Be Fabbed By TSMC

AMD CEO Lisa Su has announced that second-generation "Rome" EPYC CPU that the company is wrapping up work on is being produced out at TSMC. This is a notable departure from how things have gone for AMD with the Zen 1 generation, as GlobalFoundries has produced all of AMD's Zen CPUs, both for consumer Ryzen and professional EPYC parts.

[...] As it stands, AMD seems rather optimistic about how things are currently going. Rome silicon is already back in the labs, and indeed AMD is already sampling the parts to certain partners for early validation. Which means AMD remains on track to launch their second-generation EPYC processors in 2019.

[...] Ultimately however if they are meeting their order quota from GlobalFoundries, then AMD's situation is ultimately much more market driven: which fab can offer the necessary capacity and performance, and at the best prices. Which will be an important consideration as GlobalFoundries has indicated that it may not be able to keep up with 7nm demand, especially with the long manufacturing process their first-generation DUV-based 7nm "7LP" process requires.

See also: No 16-core AMD Ryzen AM4 Until After 7nm EPYC Launch (2019)

Related: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
Cray CS500 Supercomputers to Include AMD's Epyc as a Processor Option
AMD Returns to the Datacenter, Set to Launch "7nm" Radeon Instinct GPUs for Machine Learning in 2018
AMD Ratcheting Up the Pressure on Intel
More on AMD's Licensing of Epyc Server Chips to Chinese Companies

Original Submission

GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack 15 comments

GlobalFoundries has halted development of its "7nm" low power node, will fire 5% of its staff, and will also halt most development of smaller nodes (such as "5nm" and "3nm"):

GlobalFoundries on Monday announced an important strategy shift. The contract maker of semiconductors decided to cease development of bleeding edge manufacturing technologies and stop all work on its 7LP (7 nm) fabrication processes, which will not be used for any client. Instead, the company will focus on specialized process technologies for clients in emerging high-growth markets. These technologies will initially be based on the company's 14LPP/12LP platform and will include RF, embedded memory, and low power features. Because of the strategy shift, GF will cut 5% of its staff as well as renegotiate its WSA and IP-related deals with AMD and IBM. In a bid to understand more what is going on, we sat down with Gary Patton, CTO of GlobalFoundries.

[...] Along with the cancellation of the 7LP, GlobalFoundries essentially canned all pathfinding and research operations for 5 nm and 3 nm nodes. The company will continue to work with the IBM Research Alliance (in Albany, NY) until the end of this year, but GlobalFoundries is not sure it makes sense to invest in R&D for 'bleeding edge' nodes given that it does not plan to use them any time soon. The manufacturer will continue to cooperate with IMEC, which works on a broader set of technologies that will be useful for GF's upcoming specialized fabrication processes, but obviously it will refocus its priorities there as well (more on GF's future process technologies later in this article).

So, the key takeaway here is that while the 7LP platform was a bit behind TSMC's CLN7FF when it comes to HVM – and GlobalFoundries has never been first to market with leading edge bulk manufacturing technologies anyway – there were no issues with the fabrication process itself. Rather there were deeper economic reasons behind the decision.

GlobalFoundries would have needed to use deep ultraviolet (DUV) instead of extreme ultraviolet (EUV) lithography for its initial "7nm" chips. It would have also required billions of dollars of investment to succeed on the "7nm" node, only to make less "7nm" chips than its competitors. The change in plans will require further renegotiation of GlobalFoundries' and AMD's Wafer Supply Agreement (WSA).

Meanwhile, AMD will move most of its business over to TSMC, although it may consider using Samsung:

TSMC's "5nm" (CLN5FF) Process On-Track for High-Volume Manufacturing in 2020 9 comments

TSMC's 5nm EUV Making Progress: Process design kits, design rule manual, electronic design automation tools, 3rd Party IP Ready

TSMC[*] this week said that it has completed development of tools required for design of SoCs that are made using its 5 nm (CLN5FF, N5) fabrication technology. The company indicated that some of its alpha customers (which use pre-production tools and custom designs) had already started risk production of their chips using its N5 manufacturing process, which essentially means that the technology is on-track for high-volume manufacturing (HVM) in 2020.

TSMC's N5 is the company's 2nd generation fabrication technology that uses both deep ultraviolet (DUV) as well as extreme ultraviolet (EUV) lithography. The process can use EUVL on up to 14 layers (a tangible progress from N7+, which uses EUVL on four non-critical layers) to enable significant improvements in terms of density. TSMC says that when compared to N7 (1st Gen 7 nm, DUV-only), N5 technology will allow chip developers to shrink die area of their designs by ~45%, making transistor density ~1.8x higher. It will also increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).

[*] TSMC - Taiwan Semiconductor Manufacturing Corporation

Same chip(let) size? Approximately double the core count.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April

Related: Samsung Plans to Make "5nm" Chips Starting in 2019-2020
ASML Plans to Ship 30 Extreme Ultraviolet Lithography (EUV) Scanners in 2019

Original Submission

Another Step Toward the End of Moore's Law 16 comments

At the end of March, two semiconductor manufacturing titans climbed another rung on the ladder of Moore's Law.

Taiwan Semiconductor (TSMC) announced 5nm manufacturing of at-risk-production while Samsung announced its own 5nm manufacturing process was ready for sampling.

TSMC says its 5-nm process offers a 15 percent speed gain or a 30 percent improvement in power efficiency. Samsung is promising a 10 percent performance improvement or a 20 percent efficiency improvement

Also, "both Samsung and TSMC are offering what they're calling a 6-nm process" as a kind of stepping stone for customers with earlier availability (H2 2019) vs 5nm production.

Unfortunately, but perhaps not unexpectedly, the playing field has narrowed significantly with the progression to 5nm foundry production

GlobalFoundries gave up at 14 nm and Intel, which is years late with its rollout of an equivalent to competitors' 7 nm, is thought to be pulling back on its foundry services, according to analysts.

Samsung and TSMC remain because they can afford the investment and expect a reasonable return. Samsung was the largest chipmaker by revenue in 2018, but its foundry business ranks fourth, with TSMC in the lead. TSMC's capital expenditure was $10 billion in 2018. Samsung expects to nearly match that on a per-year basis until 2030.

Can the industry function with only two companies capable of the most advanced manufacturing processes? "It's not a question of can it work?" says [G. Dan Hutcheson, at VLSI Research]. "It has to work."

According to Len Jelinek, a semiconductor-manufacturing analyst at IHS Markit. "As long as we have at least two viable solutions, then the industry will be comfortable"

There may only be two left, but neither company is sitting still:

This discussion has been archived. No new comments can be posted.
Display Options Threshold/Breakthrough Mark All as Read Mark All as Unread
The Fine Print: The following comments are owned by whoever posted them. We are not responsible for them in any way.
  • (Score: 0) by Anonymous Coward on Wednesday October 10 2018, @09:34PM

    by Anonymous Coward on Wednesday October 10 2018, @09:34PM (#747149)

    If 11 nm is good enough for Intel, it sho u ld be good enough for you.

  • (Score: 0) by Anonymous Coward on Wednesday October 10 2018, @09:39PM (8 children)

    by Anonymous Coward on Wednesday October 10 2018, @09:39PM (#747156)

    Can't someone come up with a more meaningful way to refer to these technologies?

    To start: There is nothing particular on these chips that is "7 nm" or "5 nm" in size, but "5 nm" is going to have generally smaller components than "7 nm" and thus require less power to perform the same task. So how about using a standard task and the power consumption for that?

    • (Score: 2) by bob_super on Wednesday October 10 2018, @10:03PM

      by bob_super (1357) on Wednesday October 10 2018, @10:03PM (#747167)

      The numbers have been based on reflecting Moore's law (ish, I know), with a 2x gain every two generations, and marketing rounding the sqrt(2) every generation.
      Which was perfectly fine as long as 1) Moore's law was in full swing, 2) Intel was the unquestionable process leader
      Since condition 2) ran into an EUV problem, we are regularly reminded that "those numbers are artificial, near meaningless, and don't trust those evil marketing guys from Taiwan who would have you believe that their process is better than ours".

    • (Score: 2) by takyon on Wednesday October 10 2018, @10:12PM (3 children)

      by takyon (881) <{takyon} {at} {}> on Wednesday October 10 2018, @10:12PM (#747170) Journal

      Intel came up with "millions of transistors per square millimeter" [] as one metric.

      [SIG] 10/28/2017: Soylent Upgrade v14 []
      • (Score: 0) by Anonymous Coward on Wednesday October 10 2018, @10:16PM

        by Anonymous Coward on Wednesday October 10 2018, @10:16PM (#747172)

        What is that in hogsheads per furlong?

      • (Score: 2) by FatPhil on Wednesday October 10 2018, @11:21PM

        by FatPhil (863) <> on Wednesday October 10 2018, @11:21PM (#747197) Homepage
        These nm measurements are basically the scaled reciprocal of those (which is there an area measurement), with a scale factor determined about a decade back when the number did correspond to some feature length.

        So if you see a halving of the 'nm' measurement, you'll be getting a double of the density, not a quadrupling of it.
        Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves
      • (Score: 2) by DannyB on Thursday October 11 2018, @03:38PM

        by DannyB (5839) Subscriber Badge on Thursday October 11 2018, @03:38PM (#747464) Journal

        For ages I've occasionally heard CPU power expressed (without numbers) in horsepower. "We need a box with more horsepower." "The new processors have more horsepower." Etc.

        I suppose that would be the amount of computing that one horse can do in one day? Or somesuch definition.

        Trump is a poor man's idea of a rich man, a weak man's idea of a strong man, and a stupid man's idea of a smart man.
    • (Score: 2) by VLM on Wednesday October 10 2018, @10:55PM (1 child)

      by VLM (445) on Wednesday October 10 2018, @10:55PM (#747184)

      It means something VERY hand wavy like the radius of a one bit cell in a SDRAM which is a weird way to spec a CPU because CPUs are not very dense.

      If I did the math in my head correctly (quite likely wrong) a "10 nm process" Apple A11 has 4E9 transistors on 88 sq mm which is something like 88e-3 ** 0.5 / 4e9 ** 0.5 * 1e9 results in the average transistor having a cell about 4690 nm to live in. Which seems wrong somehow, but it is after all a CPU even if most of the transistors are on chip cache ram.

      Anyway dram is tightly packed and if you had an old fashioned 45 nm process that gets the figure of merit F. Then the wordline pitch will be 2F and bitline pitch 2F aka 90 nm and the cell area is 6 F squared and all that. There are immense spreadsheets calculating everything off "F". Thats capacitor over bitline where the caps are double sided vertical tubesies with something like 4 interconnect layers (or do you need five? I'm tired). Theres a boring as hell 100+ page PDF of a power point that I have somewhere from some memory producer but they all have stuff like this if you google for it. The point is for any "half pitch feature number" F there are plug and chug spreadsheets to make ridiculously accurate estimates for how much space a SDRAM chip of capacity X would require hence how many you get from a single slice of expensive silicon and also you can predict failure rates based on size and heat and all kinds of BS. They even model how far the wire bonder has to move across the die in their spreadsheets, supposedly..

      I don't know if there's anything quite like this in FPGAs (at least in public) where you can take the funky F value and turn it into an Alterra ALM element will be 85.323F in width and 10F in length or each MLAB memory-logic clump (I think there's a more professional term than clump, but whatevs) is 259F in width or similar enough. It works for memory, it doesn't work for CPUs, it MIGHT work for FPGAs.

      You are correct its much like seconds of specific impulse for a rocket motor where you can predict and model fairly accurately which engine is more gooder, but it doesn't mean very much. A second of specific impulse is something like the rocket could levitate fuel for that many seconds if it didn't burn fuel while levitating in a non-calculus sorta way, kinda. Or if you wanted to levitate a bucket of fuel (in the sense of total mass, including oxidizer) then it would burn 1/Isp of the fuel to levitate every second. Levitate as in apply 1G. The official definition is a figure of merit that falls out as seconds.

      In summary it means very little for a CPU but for memory bean counters they can drop F into a spreadsheet and forecast tiny details into infinity. CPU guys not so much because CPUs are internally so random and confusing. Other guys (FPGAs and stuff) in between usefulness.

      • (Score: 0) by Anonymous Coward on Thursday October 11 2018, @12:02PM

        by Anonymous Coward on Thursday October 11 2018, @12:02PM (#747396)

        Isp on a rocket motor is much simpler and more useful than that. It is basically how many pounds of thrust you get for each pound of fuel you burn per second.
        Isp = Thrust (pounds) /Fuel consumption (pounds/sec)
        The reason pounds are still used is that they cancel out nicely*, leaving you with a single number that is a pretty good metric for how good your motor is.

        Another way to look at it is one pound of fuel will provide one pound of thrust for Isp seconds.

        *they shouldn't really, one is Force, the other should be Mass, but if you weigh your fuel on the ground it works.

    • (Score: 3, Informative) by richtopia on Thursday October 11 2018, @05:29AM

      by richtopia (3160) on Thursday October 11 2018, @05:29AM (#747295) Homepage Journal

      ASML has come up with "standard node", and ASML should know process nodes better than anyone: they are making the litho tools after all!

      The formula is contacted poly pitch (CPP) multiplied by minimum metal pitch (MMP), and here is an article discussing it (and the author's alternative which adds tracks to the formula): []

      Looking at the charts we see what is generally accepted: Intel's 10nm node is comparable with everyone else's 7nm node.

  • (Score: 2) by JoeMerchant on Wednesday October 10 2018, @10:46PM

    by JoeMerchant (3937) on Wednesday October 10 2018, @10:46PM (#747183)

    Maybe early production is always referred to as Risk Production in this industry.

    In our industry, when we build "at risk" it means we've totally short-cut lots of procedural stuff and there's a good chance that something's not going to work out for final production, but we're building a (usually small) run anyway "at risk" on the chance that everything is going to be fine and we get a win in the form of early prototypes, or even if the parts don't work we get earlier identification of what we've got to fix for final production and what we appear to be doing right already.

    🌻🌻 []
  • (Score: 2) by bzipitidoo on Thursday October 11 2018, @12:47AM (1 child)

    by bzipitidoo (4388) on Thursday October 11 2018, @12:47AM (#747216) Journal

    I've always wondered whether the scale could have been reduced a lot faster. Once the basic transistor technology was proven in the 1960s, what was to stop us from reaching 22nm in the 1990s, the moment the blue LED was developed?

    But I suppose there were a lot of little improvements that depended on previous improvements, in a long chain and web, sort of like advancement from Bronze Working to Railroad in Sid Meier's Civilization.

    • (Score: 2) by Azuma Hazuki on Thursday October 11 2018, @12:56AM

      by Azuma Hazuki (5086) on Thursday October 11 2018, @12:56AM (#747225) Journal

      22nm is abuit 1/20th the length of a wave of blue light. "EUV" itself is rather euphemistic; we're in hard X-ray territory here, with all that that implies.

      I am "that girl" your mother warned you about...