TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April

TSMC to Build 7nm Process Test Chips in Q1 2018 4 comments

https://www.anandtech.com/show/11832/tsmc-teams-up-with-arm-and-cadence-to-build-7-nm-chip-in-q1-2018

TSMC has announced plans to build its first test chips for data center applications using its 7 nm fabrication technology. The chip will use compute cores from ARM, a Cache Coherent Interconnect for Accelerators (CCIX), and IP from Cadence (a DDR4 memory controller, PCIe 3.0/4.0 links). Given the presence of the CCIX bus and PCIe 4.0 interconnects, the chip will be used to show the benefits of TSMC's 7 nm process primarily for high-performance compute (HPC) applications. The IC will be taped out in early Q1 2018.
The 7 nm test chips from TSMC will be built mainly to demonstrate capabilities of the semiconductor manufacturing technology for performance-demanding applications and find out more about peculiarities of the process in general. The chip will be based on ARMv8.2 compute cores featuring DynamIQ, as well as a CMN-600 interconnect bus for heterogeneous multi-core CPUs. ARM and TSMC do not disclose which cores they are going to use for the device - the Cortex A55 and A75 are natural suspects, but that's speculation at this point. The new chip will also have a DDR4 memory controller as well as PCI Express 3.0/4.0 links, CCIX bus and peripheral IP buses developed by Cadence. The CCIX bus will be used to connect the chip to Xilinx's Virtex UltraScale+ FPGAs (made using a 16 nm manufacturing technology), so in addition to implementation of its cores using TSMC's 7 nm fabrication process, ARM will also be able to test Cadence's physical implementation of the CCIX bus for accelerators, which is important for future data center products.

Original Submission

TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020 3 comments

takyon writes:

Taiwan Semiconductor Manufacturing Company (TSMC) plans to make so-called "5nm" chips starting in early 2020:

TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC's 5 nm process starting from early 2020. When all three phases of the manufacturing facility are completed, its wafer starts capacity will exceed one million 300-mm wafers per year, comparable with other three GigaFabs operated by TSMC.
TSMC's Fab 18 will be located in Tainan (in the Southern Taiwan Science Park), and will be built in three phases. The construction of the first phase or segment of the building will be completed in about a year from now, after which TSMC will move in equipment sometime in early 2019. In about two years from now, the company expects to start volume production of chips using its 5 nm process technology at the Fab 18/phase 1. Construction of the second and the third phases will commence in Q3 2018 and Q3 2019. The two phases will start volume production in 2020 and 2021, respectively.

Extreme ultraviolet (EUV) lithography could be used to make "7nm" chips, but not "5nm" yet.

Original Submission

"3nm" Test Chip Taped Out by Imec and Cadence 13 comments

takyon writes:

Imec and Cadence Tape Out Industry's First 3nm Test Chip

The world-leading research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. today announced that its extensive, long-standing collaboration has resulted in the industry's first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.

A tape-out is the final step before the design is sent to be fabricated.

Meanwhile, Imec is looking towards nodes smaller than "3nm":

[...] industry is pinpointing and narrowing down the transistor options for the next major nodes after 3nm. Those two nodes, called 2.5nm and 1.5nm, are slated to appear in 2027 and 2030, respectively, according to the International Technology Roadmap for Semiconductors (ITRS) version 2.0. Another organization, Imec, is more aggressive with the timetable, saying that 2.5nm or thereabouts will arrive by 2024.

Also at EE Times.

Original Submission

TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process 2 comments

takyon writes:

TSMC Details 5 nm Process Tech: Aggressive Scaling, But Thin Power and Performance Gains

At a special event last week, TSMC announced the first details about its 5 nm manufacturing technology that it plans to use sometime in 2020. CLN5 will be the company's second fabrication process to use extreme ultraviolet (EUV) lithography, which is going to enable TSMC to aggressively increase its transistor density versus prior generations. However, when it comes to performance and power improvements, the gains do not look very significant.
Just like other fabs, TSMC will gradually ramp up usage of ASML's Twinscan NXE:3400 EUV step and scan systems. Next year TSMC will start using EUV tools to pattern non-critical layers of chips made using its second-gen 7 nm fabrication technology (CLN7FF+). Usage of EUV for non-critical layers will bring a number of benefits to the CLN7FF+ vs. the original CLN7FF process, but the advantages will be limited: TSMC expects the CLN7FF+ to offer a 20% higher transistor density and a 10% lower power consumption at the same complexity and frequency when compared to the CLN7FF. TSMC's 5 nm (CLN5) technology will increase the usage of EUV tools and this will bring rather massive advantages when it comes to transistor density: TSMC is touting a 1.8x higher transistor density (~45% area reduction) when compared to the original CLN7FF, but it will only enable a 15% frequency gain (at the same complexity and power) or a 20% power reduction (at the same frequency and complexity). With the CLN5, TSMC will also offer an Extremely Low Threshold Voltage (ELTV) option that will enable its clients to increase frequencies of their chips by 25%, but the manufacturer has yet to describe the tech in greater detail.

1.8x higher transistor density and up to 15% frequency gain or 20% power reduction? You should be thankful you're getting anything!

Original Submission

TSMC Will Make AMD's "7nm" Epyc Server CPUs 4 comments

takyon writes:

AMD "Rome" EPYC CPUs to Be Fabbed By TSMC

AMD CEO Lisa Su has announced that second-generation "Rome" EPYC CPU that the company is wrapping up work on is being produced out at TSMC. This is a notable departure from how things have gone for AMD with the Zen 1 generation, as GlobalFoundries has produced all of AMD's Zen CPUs, both for consumer Ryzen and professional EPYC parts.
[...] As it stands, AMD seems rather optimistic about how things are currently going. Rome silicon is already back in the labs, and indeed AMD is already sampling the parts to certain partners for early validation. Which means AMD remains on track to launch their second-generation EPYC processors in 2019.
[...] Ultimately however if they are meeting their order quota from GlobalFoundries, then AMD's situation is ultimately much more market driven: which fab can offer the necessary capacity and performance, and at the best prices. Which will be an important consideration as GlobalFoundries has indicated that it may not be able to keep up with 7nm demand, especially with the long manufacturing process their first-generation DUV-based 7nm "7LP" process requires.

Original Submission

GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack 15 comments

takyon writes:

GlobalFoundries has halted development of its "7nm" low power node, will fire 5% of its staff, and will also halt most development of smaller nodes (such as "5nm" and "3nm"):

GlobalFoundries on Monday announced an important strategy shift. The contract maker of semiconductors decided to cease development of bleeding edge manufacturing technologies and stop all work on its 7LP (7 nm) fabrication processes, which will not be used for any client. Instead, the company will focus on specialized process technologies for clients in emerging high-growth markets. These technologies will initially be based on the company's 14LPP/12LP platform and will include RF, embedded memory, and low power features. Because of the strategy shift, GF will cut 5% of its staff as well as renegotiate its WSA and IP-related deals with AMD and IBM. In a bid to understand more what is going on, we sat down with Gary Patton, CTO of GlobalFoundries.
[...] Along with the cancellation of the 7LP, GlobalFoundries essentially canned all pathfinding and research operations for 5 nm and 3 nm nodes. The company will continue to work with the IBM Research Alliance (in Albany, NY) until the end of this year, but GlobalFoundries is not sure it makes sense to invest in R&D for 'bleeding edge' nodes given that it does not plan to use them any time soon. The manufacturer will continue to cooperate with IMEC, which works on a broader set of technologies that will be useful for GF's upcoming specialized fabrication processes, but obviously it will refocus its priorities there as well (more on GF's future process technologies later in this article).
So, the key takeaway here is that while the 7LP platform was a bit behind TSMC's CLN7FF when it comes to HVM – and GlobalFoundries has never been first to market with leading edge bulk manufacturing technologies anyway – there were no issues with the fabrication process itself. Rather there were deeper economic reasons behind the decision.

GlobalFoundries would have needed to use deep ultraviolet (DUV) instead of extreme ultraviolet (EUV) lithography for its initial "7nm" chips. It would have also required billions of dollars of investment to succeed on the "7nm" node, only to make less "7nm" chips than its competitors. The change in plans will require further renegotiation of GlobalFoundries' and AMD's Wafer Supply Agreement (WSA).

Meanwhile, AMD will move most of its business over to TSMC, although it may consider using Samsung:

TSMC's "5nm" (CLN5FF) Process On-Track for High-Volume Manufacturing in 2020 9 comments

takyon writes:

TSMC's 5nm EUV Making Progress: Process design kits, design rule manual, electronic design automation tools, 3rd Party IP Ready

TSMC[*] this week said that it has completed development of tools required for design of SoCs that are made using its 5 nm (CLN5FF, N5) fabrication technology. The company indicated that some of its alpha customers (which use pre-production tools and custom designs) had already started risk production of their chips using its N5 manufacturing process, which essentially means that the technology is on-track for high-volume manufacturing (HVM) in 2020.
TSMC's N5 is the company's 2nd generation fabrication technology that uses both deep ultraviolet (DUV) as well as extreme ultraviolet (EUV) lithography. The process can use EUVL on up to 14 layers (a tangible progress from N7+, which uses EUVL on four non-critical layers) to enable significant improvements in terms of density. TSMC says that when compared to N7 (1st Gen 7 nm, DUV-only), N5 technology will allow chip developers to shrink die area of their designs by ~45%, making transistor density ~1.8x higher. It will also increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).

[*] TSMC - Taiwan Semiconductor Manufacturing Corporation

Same chip(let) size? Approximately double the core count.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April

Original Submission

Another Step Toward the End of Moore's Law 16 comments

RandomFactor writes:

At the end of March, two semiconductor manufacturing titans climbed another rung on the ladder of Moore's Law.

Taiwan Semiconductor (TSMC) announced 5nm manufacturing of at-risk-production while Samsung announced its own 5nm manufacturing process was ready for sampling.

TSMC says its 5-nm process offers a 15 percent speed gain or a 30 percent improvement in power efficiency. Samsung is promising a 10 percent performance improvement or a 20 percent efficiency improvement

Also, "both Samsung and TSMC are offering what they're calling a 6-nm process" as a kind of stepping stone for customers with earlier availability (H2 2019) vs 5nm production.

Unfortunately, but perhaps not unexpectedly, the playing field has narrowed significantly with the progression to 5nm foundry production

GlobalFoundries gave up at 14 nm and Intel, which is years late with its rollout of an equivalent to competitors' 7 nm, is thought to be pulling back on its foundry services, according to analysts.
Samsung and TSMC remain because they can afford the investment and expect a reasonable return. Samsung was the largest chipmaker by revenue in 2018, but its foundry business ranks fourth, with TSMC in the lead. TSMC's capital expenditure was $10 billion in 2018. Samsung expects to nearly match that on a per-year basis until 2030.
Can the industry function with only two companies capable of the most advanced manufacturing processes? "It's not a question of can it work?" says [G. Dan Hutcheson, at VLSI Research]. "It has to work."

According to Len Jelinek, a semiconductor-manufacturing analyst at IHS Markit. "As long as we have at least two viable solutions, then the industry will be comfortable"

There may only be two left, but neither company is sitting still:

Samsung has already announced 3nm fab plans and released design kits.
TSMC has gained approval for the construction of a 3nm factory next to its 5nm fab.

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