Early to embed and early to rise? Western Digital drops veil on SweRVy RISC-V based designs
Western Digital today finally flashed the results of its vow to move a billion controller cores to RISC-V designs. WD said last year it needed an open and extensible CPU architecture for its purpose-built drive controllers and other devices. As we explained then, no one knew for sure what processors WD has used for its disk and SSD controllers, though they was likely Arm-compatible chips – such as Arm9 and Cortex-M3 parts. It is known that the firm uses Intel CPUs with its ActiveScale archive systems and Tegile all-flash and hybrid arrays.
Last year, the disk and solid-state drive manufacturer vowed that RISC-V was its future, and today it announced the SweRV core, a networked cache coherency scheme, and a SweRV instruction set simulator.
[...] The SweRV core has a two-way superscalar design and is a 32-bit, nine-stage pipeline core, meaning several instructions can be loaded at once and execute simultaneously to save time. It is also an in-order core, whose relative single core performance (a simulated 4.9 CoreMark/Mhz) is expected to exceed that of many out-of-order cores, such as the Arm Cortex A15 (actual 4.72CoreMark/Mhz). Clock speeds go up to 1.8Ghz and it will be built on a
28mm[28nm] CMOS process technology.WD said it hopes open-sourcing the core will drive development of data-centric applications such as Internet of Things (IoT), secure processing, industrial controls and more. We understand WD's ambitions for using RISC-V CPUs go beyond disk and flash drive controllers.
Previously: Western Digital to Transition Consumption of Over One Billion Cores Per Year to RISC-V
Related: WD Announces Client NVMe SSDs with In-House Controllers
Related Stories
From a Western Digital press release:
Western Digital Corp. (NASDAQ: WDC) announced today at the 7th RISC-V Workshop that the company intends to lead the industry transition toward open, purpose-built compute architectures. In his keynote address, Western Digital's Chief Technology Officer Martin Fink expressed the company's commitment to [...] transitioning its own consumption of processors – over one billion cores per year – to RISC-V.
Western Digital is beginning to use in-house controllers in its new NVMe (Non-Volatile Memory Express) SSDs, but has confirmed that they do not contain RISC-V cores just yet:
Western Digital has announced their first client NVMe SSDs with their SanDisk 64-layer 3D TLC NAND. These drives are also the first to feature Western Digital's new in-house NVMe SSD controllers. This is a major shift in strategy away from third-party controllers (mostly Marvell) toward complete vertical integration.
The new SSDs are called the Western Digital SN720 and Western Digital SN520. Branding for these is a bit of a mess with the drives bearing the Western Digital name and model numbers that almost fit in with the HGST Ultrastar SN200 and SN260 enterprise NVMe SSDs, but the product information is on the SanDisk website and the target market is similar to that of SanDisk's business/OEM drives like the X400 and X600 SATA SSDs. Western Digital may be trying to unify and simplify their several brands, but it's a work in progress.
[...] Western Digital hasn't disclosed what kind of processor cores are used in their NVMe controllers, but they did confirm that these aren't using the RISC-V architecture—those products won't be arriving until next year at the earliest. The Western Digital NVMe controllers are probably using ARM Cortex-R cores like most SSD controllers.
Western Digital's RISC-V "SweRV" Core Design Released For Free
Western Digital has published a register-transfer level (RTL) design abstraction of its in-house designed SweRV RISC-V core. The SweRV core is one of several RISC-V projects the company as undertaken as part of their effort to spearhead the ISA, its ecosystem, and foster their own transition away from licensed, royalty-charging CPU cores. In accordance with the more open design goals of RISC-V, the publication of the high-level representation of SweTV means that third parties can use it in their own chip designs, which will popularize not only the particular core design, but also the RISC-V architecture in general.
The RTL design abstraction of Western Digital's RISC-V SweRV core is now available at GitHub. The design is licensed under the Apache 2.0 license, which is a very permissive (and non-copyleft) license that allows the core to be used free of charge, with or without modifications, and without requiring any modifications to be released in-kind. In fact the requirements of the license are quite slim; besides requiring appropriate attribution, the only other notable restriction is that third party developers cannot use Western Digital's brands to mark their work.
Previously: Western Digital to Transition Consumption of Over One Billion Cores Per Year to RISC-V
Western Digital Unveils RISC-V Controller Design
Qualcomm Invests in RISC-V Startup SiFive
Investors are zeroing in on the open standard RISC-V instruction set architecture and the processor intellectual property being developed by a batch of high-flying chip startups.
Last fall, Esperanto Technologies announced a $58 million funding round. The chip IP vendor is incorporating more than 1,000 RISC-V cores onto a single 7-nm chip. Data storage specialist Western Digital is an early investor in Esperanto, Mountain View, Calif.
This week, another RISC-V startup, SiFive, announced a $65.4 million funding round that included new investor Qualcomm Ventures. SiFive, San Mateo, Calif., has so far raised more than $125 million, and is seen as a challenger to chip IP leader Arm.
Observers note that wireless modem leader Qualcomm is among Arm's biggest customers, making its investment in SiFive intriguing. Also participating in the Series D round were existing investors Chengwei Capital of Shanghai along with Sutter Hill Ventures and Spark Capital. Intel Capital and Western Digital also were early investors.
Also at EE Times.
See also: SiFive Acquires USB 2.0 and 3.x IP Portfolio to Strengthen RISC-V SoCs
Previously: RISC-V Projects to Collaborate
SiFive and UltraSoC Partner to Accelerate RISC-V Development Through DesignShare
SiFive Introduces RISC-V Linux-Capable Multicore Processor
SiFive HiFive Unleashed Not as Open as Previously Thought
Linux Foundation and RISC-V Proponents Launch CHIPS Alliance
Separately, a handful of RISC-V proponents launched the CHIPS Alliance, a project of the Linux Foundation to develop a broad set of open-source IP blocks and tools for the instruction set architecture. Initial members include Esperanto, Google, SiFive, and Western Digital. CHIPS stands for Common Hardware for Interfaces, Processors, and Systems.
Esperanto Technologies and SiFive look like the names to watch.
Related: First Open Source RISC-V Implementations Become Available
Western Digital Unveils RISC-V Controller Design
Raspberry Pi Foundation Announces RISC-V Foundation Membership
Western Digital Publishes RISC-V "SweRV" Core Design Under Apache 2.0 License
(Score: 1, Insightful) by Anonymous Coward on Wednesday December 05 2018, @03:37PM (15 children)
I had more ambitious hopes for RISC-V computing systems, but as usual, they've basically dissolved into the ether of vaporware.
Slowly, but surely. That's the only way anything ever happens.
(Score: 2) by takyon on Wednesday December 05 2018, @03:44PM (2 children)
If it wasn't for this news, RISC-V would be worse off. Bring on the billions of cores.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2, Informative) by Anonymous Coward on Wednesday December 05 2018, @04:00PM (1 child)
There are currently several microcontroller-class RISC-V boards avaliable, such as the HiFive and GAP8 (seemingly with a focus on computer vision): https://www.cnx-software.com/?s=Risc-v [cnx-software.com]
Further, there is some recent and interesting work being done on a software/vulkan-based RISC-V graphics card that even has some initial funding: https://www.phoronix.com/scan.php?page=news_item&px=Libre-RISC-V-Performance-Target [phoronix.com]
Slowly progress is being made and there is opportunity to contribute. I believe both gcc and lvm have matured their architecture targets and virtualization backends are supporting it as well.
(Score: 2) by driverless on Thursday December 06 2018, @10:33AM
Have you ever tried to buy a RISC-V system, specifically a non-toy one capable of self-hosting a Linux development environment for dev work? Unless something new has appeared in the last month or so, you can buy a full x86 server for less than the cost of the most rudimentary RISC-V system. It may be new and hip and whatever, but you're paying an arm and a leg for it.
(Score: 1, Insightful) by Anonymous Coward on Wednesday December 05 2018, @05:02PM (10 children)
you're being very unrealistic. this is good news. a big company using riscv in such a big way and being good community members at the same time is a good first step.
(Score: 0) by Anonymous Coward on Wednesday December 05 2018, @05:15PM
It's also irritating.
(Score: 2) by DannyB on Wednesday December 05 2018, @05:24PM (8 children)
Yes, a good first step.
A good second step would be for an education focused board, like a Raspberry Pi type thing, to use this chip. That would spur more software development. And get it into the hands of students and hobbyists.
If you think a fertilized egg is a child but an immigrant child is not, please don't pretend your concerns are religious
(Score: 1, Insightful) by Anonymous Coward on Wednesday December 05 2018, @06:12PM (7 children)
Did Musk get an electric go-cart into the hands of campus-weary students or mobile hobbyists? No. He built a goddamn, mother-fucking Hot Rod for the wealthy players.
We need a FOSH GPU as a RISC-V extension—something with some serious computing ability; something which is expensive.
Otherwise, ain't nobody gonna be interested.
(Score: 4, Insightful) by bob_super on Wednesday December 05 2018, @06:24PM (6 children)
To get a processor to be popular, it needs code.
Remember Alpha, Itanium, and so many others ? Lottsa power, but very expensive and therefore only doing a few specific things.
If you're gonna go incompatible and ask for a lot of money, the people willing to shell out that money need instant amazing benefits, or you don't get funding for OS and program development. That's getting harder and harder to do against the x64 juggernaut.
ARM started small, and took over the computing world, supported by companies looking to save power, and happy to get developing for cheap.
(Score: 0) by Anonymous Coward on Wednesday December 05 2018, @06:38PM (3 children)
It's in the name: General-purpose computing is, well, a large and difficult arena.
That's why you concentrate on a niche market first. You computer folks keep trying to go for the low-end niche market (e.g., IoT crap), which the market keeps telling you isn't real; I'm suggesting you instead go for a high-end niche market, like GPUs.
(Score: 2) by bob_super on Wednesday December 05 2018, @07:01PM (2 children)
Might be because the established players are throwing billions at the high-end, hiring very smart people and patenting all the math and Si tricks those can think of, so kicking their ass is far from cheap and trivial.
It's a bit like my startup: When you provide equipment above a certain grade, customers expect (demand) a lot of legacy features to be implemented and be somewhat familiar. That takes a lot of resources, even will all the open code available these days.
(Score: 0) by Anonymous Coward on Wednesday December 05 2018, @07:30PM (1 child)
Kicking their ass on the high end isn't even near what's required - you just have to be competetive with the run-of-the-mill stuff, while ATTRACTING the high-end money people. Consumers are fickle.
(Score: 2) by bob_super on Wednesday December 05 2018, @08:04PM
If you're new and just "competitive", you need to be cheaper. If you're better, you can command the high-end margins.
You need those margins to get anywhere, because even being "competitive" on the "high-end" against dominant established players requires a lot of resources, and gaining market share is even harder.
(Score: 0) by Anonymous Coward on Thursday December 06 2018, @03:51AM
Progress is being made. Thousands of packages in Debian run on riscV:
https://people.debian.org/~mafm/posts/2018/20180402_debian-gnulinux-port-for-risc-v-64-bit-riscv64-in-debian-infrastructure-debian-ports/ [debian.org]
(Score: 0) by Anonymous Coward on Thursday December 06 2018, @04:21PM
There were even relatively cheap (1.5-2x the cost of x86) alpha motherboards/processors in the late 1990s.
What killed Alpha was the Compaq->HP merger and the decision to collaborate with Intel on a PA-RISC successor rather than getting Alpha onto better processes. The Alpha cores at the time better than Intel, but HP/Compaq's later treatment of them priced them out of mindshare and market, before killing them to focus on Itanium, even when it became obvious itanium was a boondoggle that would have better resulted in backpedalling to either PA-RISC or Alpha (which had core designs which exceeded the performance of Itanium if they had been allowed to go into mass production.)
If you have any doubt about this, go look into the Chinese supercomputers from a few years back that used Alpha derived architecture for the floating point processing. I forget if it was the same or a different system, but they also used sparc cores as the i/o backbone for filling the FLOP cores on one of their supercomputers as well.
Consolidation and Intel's behavior damaged the tech industry in ways a lot of people still don't realize. The current spate of Spectre vulnerabilities is a prime example, since the standardization of little endian and speculative execution for processors has left it much easier to craft exploit code that works similarly everywhere, rather than a diverse assortment of hardware with low lever differences that defy devious optimizations.
(Score: 2) by EETech1 on Wednesday December 05 2018, @07:28PM
https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/risc-v-summit-preview [cadence.com]
https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/risc-v [cadence.com]
(Score: 2, Funny) by Anonymous Coward on Wednesday December 05 2018, @03:56PM (9 children)
Fabricated in a 28mm process? Millimetres?
My CPU so fat she got several Yomamas in decaying orbits!
On the plus side, rad-hardening will not be on the trouble sheet for NASA adoption ...
(Score: 0) by Anonymous Coward on Wednesday December 05 2018, @04:05PM
Even in the 1960s they were using 60 micron process, so can you explain why this would be so much larger? I am a hair stylist.
https://en.wikichip.org/wiki/50_%C2%B5m_lithography_process [wikichip.org]
(Score: 4, Funny) by takyon on Wednesday December 05 2018, @04:07PM (2 children)
fixed.modernized.[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by DannyB on Wednesday December 05 2018, @05:25PM
Fixed or repaired in the sense that I took my cat to the vet to be 'repaired'.
If you think a fertilized egg is a child but an immigrant child is not, please don't pretend your concerns are religious
(Score: 2) by bob_super on Wednesday December 05 2018, @06:14PM
9.34 atto-light-seconds or 858 nano-light-caesium-transitions
Interestingly, for the metric-haters, a light-caesium seems to be 32.6mm, or about an inch and a quarter.
(Score: 2) by Freeman on Wednesday December 05 2018, @05:06PM (2 children)
I was 50/50 typo or poor description of chip size. So, a typo or some marketing person having no idea what they were talking about when they said nanometer.
Joshua 1:9 "Be strong and of a good courage; be not afraid, neither be thou dismayed: for the Lord thy God is with thee"
(Score: 5, Funny) by nitehawk214 on Wednesday December 05 2018, @05:25PM (1 child)
You were a typo?
Did a grammar nazi put you into a consternation camp?
"Don't you ever miss the days when you used to be nostalgic?" -Loiosh
(Score: 1, Funny) by Anonymous Coward on Wednesday December 05 2018, @08:51PM
And they put him in contraction!
(Score: 0) by Anonymous Coward on Wednesday December 05 2018, @06:17PM (1 child)
Hey what's six orders of magnitude between friends?!
(Score: 4, Funny) by martyb on Thursday December 06 2018, @01:41AM
A *very* safe distance?
=)
Wit is intellect, dancing.