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posted by Fnord666 on Friday December 14 2018, @01:55AM   Printer-friendly [Skip to comment(s)]
from the latest-and-greatest dept.

Intel has announced new developments at its Architecture Day 2018:

Sunny Cove, built on 10nm, will come to market in 2019 and offer increased single-threaded performance, new instructions, and 'improved scalability'. Intel went into more detail about the Sunny Cove microarchitecture, which is in the next part of this article. To avoid doubt, Sunny Cove will have AVX-512. We believe that these cores, when paired with Gen11 graphics, will be called Ice Lake.

Willow Cove looks like it will be a 2020 core design, most likely also on 10nm. Intel lists the highlights here as a cache redesign (which might mean L1/L2 adjustments), new transistor optimizations (manufacturing based), and additional security features, likely referring to further enhancements from new classes of side-channel attacks. Golden Cove rounds out the trio, and is firmly in that 2021 segment in the graph. Process node here is a question mark, but we're likely to see it on 10nm and or 7nm. Golden Cove is where Intel adds another slice of the serious pie onto its plate, with an increase in single threaded performance, a focus on AI performance, and potential networking and AI additions to the core design. Security features also look like they get a boost.

Intel says that GT2 Gen11 integrated graphics with 64 execution units will reach 1 teraflops of performance. It compared the graphics solution to previous-generation GT2 graphics with 24 execution units, but did not mention Iris Plus Graphics GT3e, which already reached around 800-900 gigaflops with 48 execution units. The GPU will support Adaptive Sync, which is the standardized version of AMD's FreeSync, enabling variable refresh rates over DisplayPort and reducing screen tearing.

Intel's upcoming discrete graphics cards, planned for release around 2020, will be branded Xe. Xe will cover configurations from integrated and entry-level cards all the way up to datacenter-oriented products.

Like AMD, Intel will also organize cores into "chiplets". But it also announced FOVEROS, a 3D packaging technology that will allow it to mix chips from different process nodes, stack DRAM on top of components, etc. A related development is Intel's demonstration of "hybrid x86" CPUs. Like ARM's big.LITTLE and DynamIQ heterogeneous computing architectures, Intel can combine its large "Core" with smaller Atom cores. In fact, it created a 12mm×12mm×1mm SoC (compare to a dime coin which has a radius of 17.91mm and thickness of 1.35mm) with a single "Sunny Cove" core, four Atom cores, Gen11 graphics, and just 2 mW of standby power draw.


Original Submission

Related Stories

Intel Details Lakefield CPU SoC With 3D Packaging and Big/Small Core Configuration 9 comments

Intel Lakefield SoC With Foveros 3D Packaging Previewed – 10nm Hybrid CPU Architecture Featuring Sunny Cove, Gen 11 Graphics and More

Intel Lakefield is based around Foveros technology which helps connect chips and chiplets in a single package that matches the functionality and performance of a monolithic SOC. Each die is then stacked using FTF micro-bumps on the active interposer through which TSVs are drilled to connect with solder bumps and eventually the final package. The whole SOC is just 12×12 (mm) which is 144mm2.

Talking about the SOC itself and its individual layers, the Lakefield SOC that has been previewed consists of at least four layers or dies, each serving a different purpose. The top two layers are composed of the DRAM which will supplement the processor as the main system memory. This is done through the PoP (Package on Package) memory layout which stacks two BGA DRAMs on top of each other as illustrated in the preview video. The SOC won't have to rely on socketed DRAM in this case which saves a lot of footprint on the main board.

The second layer is the Compute Chiplet with a Hybrid CPU architecture and graphics, based on the 10nm process node. The Hybrid CPU architecture has a total of five individual Cores, one of them is labeled as the Big Core which features the Sunny Cove architecture. That's the same CPU architecture that will be featured on Intel's upcoming 10nm Ice Lake processors. The Sunny Cove Core is optimized for high-performance throughput. There are also four small CPUs that are based on the 10nm process but optimized for power efficiency. The same die [has] Intel's Gen 11 graphics engine with 64 Execution Units.

[...] [Last] of all is the base die which serves as the cache and I/O block of the SOC. Labeled as the P1222 and based on a 22FFL process node, the base die comes with a low cost and low leakage design while providing a feature-rich array of I/O capabilities.

It would be nice to finally see some consumer CPUs with stacked DRAM, although the amount was not specified (8 GB?).

Intel video (1m48s). Also at Notebookcheck.

Previously: Intel Announces "Sunny Cove", Gen11 Graphics, Discrete Graphics Brand Name, 3D Packaging, and More
Intel Promises "10nm" Chips by the End of 2019, and More


Original Submission

Leaked Intel Discrete Graphics Roadmap Reveals Plans for "Seamless" Dual, Quad, and Octa-GPUs 14 comments

Intel has teased* plans to return to the discrete graphics market in 2020. Now, some of those plans have leaked. Intel's Xe branded GPUs will apparently use an architecture capable of scaling to "any number" of GPUs that are connected by a multi-chip module (MCM). The "e" in Xe is meant to represent the number of GPU dies, with one of the first products being called X2/X2:

Developers won't need to worry about optimizing their code for multi-GPU, the OneAPI will take care of all that. This will also allow the company to beat the foundry's usual lithographic limit of dies that is currently in the range of ~800mm2. Why have one 800mm2 die when you can have two 600mm2 dies (the lower the size of the die, the higher the yield) or four 400mm2 ones? Armed with One API and the Xe macroarchitecture Intel plans to ramp all the way up to Octa GPUs by 2024. From this roadmap, it seems like the first Xe class of GPUs will be X2.

The tentative timeline for the first X2 class of GPUs was also revealed: June 31st, 2020. This will be followed by the X4 class sometime in 2021. It looks like Intel plans to add two more cores [dies] every year so we should have the X8 class by 2024. Assuming Intel has the scaling solution down pat, it should actually be very easy to scale these up. The only concern here would be the packaging yield – which Intel should be more than capable of handling and binning should take care of any wastage issues quite easily. Neither NVIDIA nor AMD have yet gone down the MCM path and if Intel can truly deliver on this design then the sky's the limit.

AMD has made extensive use of MCMs in its Zen CPUs, but will reportedly not use an MCM-based design for its upcoming Navi GPUs. Nvidia has published research into MCM GPUs but has yet to introduce products using such a design.

Intel will use an MCM for its upcoming 48-core "Cascade Lake" Xeon CPUs. They are also planning on using "chiplets" in other CPUs and mixing big and small CPU cores and/or cores made on different process nodes.

*Previously: Intel Planning a Return to the Discrete GPU Market, Nvidia CEO Responds
Intel Discrete GPU Planned to be Released in 2020
Intel Announces "Sunny Cove", Gen11 Graphics, Discrete Graphics Brand Name, 3D Packaging, and More

Related: Intel Integrates LTE Modem Into Custom Multi-Chip Module for New HP Laptop
Intel Promises "10nm" Chips by the End of 2019, and More


Original Submission

Intel Reveals Three New Packaging Technologies for Stitching Multiple Dies Into One Processor 12 comments

Intel will be using a few packaging technologies to connect CPU core "chiplets":

Intel revealed three new packaging technologies at SEMICON West: Co-EMIB, Omni-Directional Interconnect (ODI) and Multi-Die I/O (MDIO). These new technologies enable massive designs by stitching together multiple dies into one processor. Building upon Intel's 2.5D EMIB and 3D Foveros tech, the technologies aim to bring near-monolithic power and performance to heterogeneous packages. For the data-center, that could enable a platform scope that far exceeds the die-size limits of single dies.

[...] Compared to interposers, which can be reticle-sized (832mm2) or even larger, [EMIB (Embedded Multi-die Interconnect Bridge)] is just a small (hence, cheap) piece of silicon. It provides the same bandwidth and energy-per-bit advantages of an interposer compared to standard package traces, which are traditionally used for multi-chip packages (MCPs), such as AMD's Infinity Fabric. (To some extent, because the PCH is a separate die, chiplets have actually been around for a very long time.)

[...] Intel showed off a concept product that contains four Foveros stacks, with each stack having eight small compute chiplets that are connected via TSVs to the base die. (So the role of Foveros there is to connect the chiplets as if it were a monolithic die.) Each Foveros stack is then interconnected via two (Co-)EMIB links with its two adjacent Foveros stacks. Co-EMIB is further used to connect the HBM and transceivers to the compute stacks.

Evidently, the cost of such a product would be enormous, as it essentially contains multiple traditional monolithic-class products in a single package. That's likely why Intel categorized it as a data-centric concept product, aimed mainly at the cloud players that are more than happy to absorb those costs in exchange for the extra performance.

[...] When they are ready, these technologies will provide Intel with powerful capabilities for the heterogeneous and data-centric era. On the client side, the benefits of advanced packaging include smaller package size and lower power consumption (for Lakefield, Intel claims a 10x SoC standby power improvement at 2.6mW). In the data center, advanced packaging will help to build very large and powerful platforms on a single package, with performance, latency, and power characteristics close to what a monolithic die would yield. The yield advantage of small chiplets and the establishment of chipset ecosystem are major drivers, too.

Also at The Register, VentureBeat, Guru3D, and PCWorld.

Related: Intel Core i7-8809G with Radeon Graphics and High Bandwidth Memory: Details Leaked
Intel Announces "Sunny Cove", Gen11 Graphics, Discrete Graphics Brand Name, 3D Packaging, and More
Intel Promises "10nm" Chips by the End of 2019, and More
Intel Details Lakefield CPU SoC With 3D Packaging and Big/Small Core Configuration
Intel's Jim Keller Promises That "Moore's Law" is Not Dead, Outlines 50x Improvement Plan


Original Submission

AMD and Intel at Computex 2019: First Ryzen 3000-Series CPUs and Navi GPU Announced 20 comments

At Computex 2019 in Taipei, AMD CEO Lisa Su gave a keynote presentation announcing the first "7nm" Navi GPU and Ryzen 3000-series CPUs. All of the products will support PCI Express 4.0.

Contrary to recent reports, AMD says that the Navi microarchitecture is not based on Graphics Core Next (GCN), but rather a new "RDNA" macroarchitecture ('R' for Radeon), although the extent of the difference is not clear. There is also no conflict with Nvidia's naming scheme; the 5000-series naming is a reference to the company's 50th anniversary.

AMD claims that Navi GPUs will have 25% better performance/clock and 50% better performance/Watt vs. Vega GPUs. AMD Radeon RX 5700 is the first "7nm" Navi GPU to be announced. It was compared with Nvidia's GeForce RTX 2070, with the RX 5700 outperforming the RTX 2070 by 10% in the AMD-favorable game Strange Brigade. Pricing and other launch details will be revealed on June 10.

AMD also announced the first five Ryzen 3000-series CPUs, all of which will be released on July 7:

CPUCores / ThreadsFrequencyTDPPrice
Ryzen 9 3900X12 / 243.8 - 4.6 GHz105 W$499
Ryzen 7 3800X8 / 163.9 - 4.5 GHz105 W$399
Ryzen 7 3700X8 / 163.6 - 4.4 GHz65 W$329
Ryzen 5 3600X6 / 123.8 - 4.4 GHz95 W$249
Ryzen 5 36006 / 123.6 - 4.2 GHz65 W$199

The Ryzen 9 3900X is the only CPU in the list using two core chiplets, each with 6 of 8 cores enabled. AMD has held back on releasing a 16-core monster for now. AMD compared the Ryzen 9 3900X to the $1,189 Intel Core i9-9920X, the Ryzen 7 3800X to the $499 Intel Core i9-9900K, and the Ryzen 7 3700X to the Intel Core i7-9700K, with the AMD chips outperforming the Intel chips in certain single and multi-threaded benchmarks (wait for the reviews before drawing any definitive conclusions). All five of the processors will come with a bundled cooler, as seen in this list.

Intel Linux Graphics Driver Adding Device Local Memory - Possible Start of Discrete GPU Bring-Up 7 comments

Submitted via IRC for Bytram

Intel Linux Graphics Driver Adding Device Local Memory - Possible Start of dGPU Bring-Up

A big patch series was sent out today amounting to 42 patches and over four thousand lines of code for introducing the concept of memory regions to the Intel Linux graphics driver. The memory regions support is preparing for device local memory with future Intel graphics products.

The concept of memory regions is being added to the Intel "i915" Linux kernel DRM driver for "preparation for upcoming devices with device local memory." The concept is about having different "regions" of memory for system memory as for any device local memory (LMEM). Today's published code also introduces a simple allocator and allowing the existing GEM memory management code to be able to allocate memory to these different memory regions. Up to now with Intel integrated graphics, they haven't had to worry about this functionality not even with their eDRAM/L4 cache of select graphics processors.

This device-local memory for future Intel GPUs is almost surely for Intel's discrete graphics cards with dedicated vRAM expected to debut in 2020. For the past several generations of Iris Pro with eDRAM, the Intel Linux driver has already supported that functionality. The patch message itself makes it clear that this is for "upcoming devices" but without enabling any hardware support at this time. This memory region code doesn't touch any of the existing hardware support such as the already mainlined Icelake "Gen 11" graphics code.

Previously: Intel Planning a Return to the Discrete GPU Market, Nvidia CEO Responds
Intel Discrete GPU Planned to be Released in 2020
Intel Announces "Sunny Cove", Gen11 Graphics, Discrete Graphics Brand Name, 3D Packaging, and More


Original Submission

AMD Plans to Stack DRAM and SRAM on Top of its Future Processors 10 comments

Ryzen Up: AMD to 3D Stack DRAM and SRAM on Processors

AMD revealed at a recent high performance computing event that it is working on new designs that use 3D-stacked DRAM and SRAM on top of its processors to improve performance.

[...] Intel whipped the covers off its Foveros 3D chip stacking technology during its recent Architecture Day event and revealed it already has a leading-edge product ready to enter production. The package consists of a 10nm CPU and an I/O chip mated with TSVs (Through Silicon Via) that connect the die through vertical electrical connections in the center of the die. Intel also added a memory chip to the top of the stack using a conventional PoP (Package on Package) implementation.

Not to be left behind, AMD is also turning its eyes toward 3D chip stacking techniques, albeit from a slightly different angle. AMD SVP and GM Forrest Norrod recently presented at the Rice Oil and Gas HPC conference and revealed that the company has its own 3D stacking intiative underway.

[...] [True] 3D stacking consists of two die (in this case, memory and a processor) placed on top of each other and connected through vertical TSV connections that mate the die directly together. These TSV connections, which transfer data between the two die at the fastest speeds possible, typically reside in the center of the die. That direct mating increases performance and reduces power consumption (all data movement requires power, but direct connections streamline the process). 3D stacking also affords density advantages.

Where are the CPUs with attached High Bandwidth Memory?

Related: Intel Announces "Sunny Cove", Gen11 Graphics, Discrete Graphics Brand Name, 3D Packaging, and More
Intel Details Lakefield CPU SoC With 3D Packaging and Big/Small Core Configuration


Original Submission

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  • (Score: 0) by Anonymous Coward on Friday December 14 2018, @02:41AM (3 children)

    by Anonymous Coward on Friday December 14 2018, @02:41AM (#774243)

    Why no stats? It just says "single threaded improvement", "new instructions", "improved scalability". That reads more like a wishlist.

    • (Score: 4, Interesting) by driverless on Friday December 14 2018, @06:13AM (2 children)

      by driverless (4770) on Friday December 14 2018, @06:13AM (#774290)

      It's not a wishlist, it's what Intel has been announcing every year now for at least five years, since they ran out of ideas on what to do in their CPUs. A lick of paint here, a minor tweak there, some graphics crap that no-one cares about because Intel can't do graphics to save themselves, and new instructions including IOMAAYXPRT, WSSXPPSSFFTY, and MPLLXNGRT that some guy in Intel's sales department thought up on the toilet this morning, or possibly later in the day, around 4:20. Shit, I've got a ten-year-old Intel quad-core CPU for which the only real differentiating factor from today's CPUs is that it has AES instructions. Which in my case, and most people's cases, are entirely superfluous. There's nothing to announce because they've run out of ideas for what to do.

      • (Score: 0) by Anonymous Coward on Friday December 14 2018, @08:18PM (1 child)

        by Anonymous Coward on Friday December 14 2018, @08:18PM (#774539)

        All the development efforts have been in the [User] Management Engine.

        • (Score: 2) by driverless on Saturday December 15 2018, @12:22AM

          by driverless (4770) on Saturday December 15 2018, @12:22AM (#774619)

          Ah, of course! Those buffer overflows and leaks don't just write themselves.

  • (Score: 2) by Runaway1956 on Friday December 14 2018, @02:58AM (14 children)

    by Runaway1956 (2926) Subscriber Badge on Friday December 14 2018, @02:58AM (#774250) Homepage Journal

    AMD and nVidia may be more expensive (or not) but I'll stick with them. For all the same reasons I don't run Intel CPU's or Intel network devices. There is nothing about Intel that I like, or that I can respect.

    --
    There is a supply side shortage of pronouns. You will take whatever you are offered.
    • (Score: 1, Flamebait) by Ethanol-fueled on Friday December 14 2018, @03:20AM

      by Ethanol-fueled (2792) on Friday December 14 2018, @03:20AM (#774255) Homepage

      Anti-Semite! Now eat our chips, Goy, they are best-served with dips like you.

    • (Score: 0) by Anonymous Coward on Friday December 14 2018, @03:21AM (11 children)

      by Anonymous Coward on Friday December 14 2018, @03:21AM (#774256)

      Intel will not be cheaper if this is true: https://www.techpowerup.com/img/iQWJhazDsExN7biT.jpg [techpowerup.com]

      Keep in mind they were showing off a 28 core 5 GHz cpu that required like 1 kW of industrial cooling for ~$10k not long ago...

      https://www.youtube.com/watch?v=ozcEel1rNKM [youtube.com]

      • (Score: 2) by takyon on Friday December 14 2018, @03:28AM (10 children)

        by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday December 14 2018, @03:28AM (#774259) Journal

        This is the newer leak: https://wccftech.com/amd-ryzen-3000-specs-prices-leaked-upto-16-cores-5-1ghz-on-am4/ [wccftech.com] which came from AdoredTV on YouTube.

        Notice the Ryzen 9 3850X, slated for May 2019? If correct, that would be AMD's "50th anniversary chip" (they were founded on May 1, 1969).

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        • (Score: 0) by Anonymous Coward on Friday December 14 2018, @03:52AM (9 children)

          by Anonymous Coward on Friday December 14 2018, @03:52AM (#774267)

          Notice the Ryzen 9 3850X, slated for May 2019? If correct, that would be AMD's "50th anniversary chip" (they were founded on May 1, 1969).

          Sorry, this didn't have the (I assume) expected impact on me. What is exceptional about this vs the rest of the craziness in these leaks?

          • (Score: 3, Interesting) by takyon on Friday December 14 2018, @04:00AM (8 children)

            by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday December 14 2018, @04:00AM (#774269) Journal

            It seems more likely to me than slapping the old "Black Edition" label on it from the Bulldozer days. It's also similar to how Intel recently released an i7-8086K commemorative chip. AMD could be copying that idea and the timing is just right.

            The YouTuber went into greater detail about why he thought his leak was accurate. You can watch it yourself if you want. Or just wait until CES in January.

            The most important point, that the top Ryzen chips will have 12 and 16 cores, has been floating around for a long time now. That was reinforced when AMD raised Threadripper 2 up to 16-32 cores despite not increasing cores per CCX on the "12nm" node. And now we know that the Epyc chips will have 64 cores using 8 chiplets. The 16-core Ryzen is a done deal.

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            [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
            • (Score: 2) by bob_super on Friday December 14 2018, @06:22PM (7 children)

              by bob_super (1357) on Friday December 14 2018, @06:22PM (#774500)

              > The 16-core Ryzen is a done deal.

              Sadly for their profits, what most of the market needs is covered by a quad-A73.

              I'm very glad for the progress (Go AMD!), by my current quad i5 is about 5 years old, and unless it kicks the bucket, it looks like it should be enough until Ryzen 4.

              • (Score: 2) by takyon on Friday December 14 2018, @07:07PM (3 children)

                by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday December 14 2018, @07:07PM (#774516) Journal

                Chicken, meet egg. Or vice versa. With core counts reaching 16 for mainstream CPUs, someone will come up with software that can take advantage of it. And don't say "bloat will do it!" because you actually have to try to waste those resources.

                I wish you luck on stretching to Ryzen 4 or 5. Maybe you can hold out until the "5nm" node for some extra gains. If you get an APU or GPU, make sure it comes with AV1 hardware decoding.

                --
                [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
              • (Score: 0) by Anonymous Coward on Friday December 14 2018, @10:06PM (2 children)

                by Anonymous Coward on Friday December 14 2018, @10:06PM (#774572)

                I think you've got it in reverse. Intel's monopoly stagnated the PC market, so people stopped coming up with cool new stuff to do with them.

                • (Score: 2) by bob_super on Friday December 14 2018, @10:36PM (1 child)

                  by bob_super (1357) on Friday December 14 2018, @10:36PM (#774581)

                  Most of the market needs a computer to check email/facebook/twitter, order on Amazon, make/watch youtube/porn, and do some basic office stuff.
                  A quad A73 is plenty for all of the above. Intel delivering more power would not have changed that much, just enabled faster spying.

                  I got a free Titan card for my PC, yet without playing the latest AAA games, I don't seem to be hurting the processor, yet I am pretty satisfied with the scene complexity compared to ten years ago.
                  I'm sure my future Ryzen 3 oe 4 will blow my socks off.

                  • (Score: 1, Insightful) by Anonymous Coward on Friday December 14 2018, @11:01PM

                    by Anonymous Coward on Friday December 14 2018, @11:01PM (#774591)

                    A quad A73 is plenty for all of the above. Intel delivering more power would not have changed that much, just enabled faster spying.

                    It isn't just delivering more power, it is also doing the same while consuming less power, or much cheaper.

                    But in general, the high core count is a qualitative difference from the gradually increasing single thread speed on 2-6 cores intel has been offering. We don't know yet who will be able to take advantage of this.

    • (Score: 4, Interesting) by takyon on Friday December 14 2018, @03:24AM

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday December 14 2018, @03:24AM (#774257) Journal

      Same here. One correction though... AMD is not more expensive than Intel. Not by $/core, not by $/performance. And that will become very apparent when they start releasing "7nm" desktop chips next year. But this list of Intel stuff still warrants a look anyway.

      To give credit where it's due, Intel dominates in low-Watt x86. Their sub-8W Celerons, Pentiums, and Atoms are pretty ubiquitous in Chromebooks and whatever the Windows equivalent is while there are basically no AMD chips in those (there are some ARM chips). I like those machines since they are light, fanless, and have great battery life. They also do pretty well with the 15 Watt laptop chips, i.e. the ones found in "ultrabooks". And then even when we factor in AMD's expected IPC and clock improvements in 2019, Intel might still be ahead in single-threaded performance across the board.

      So when I see the "hybrid x86" demo chip, that's pretty interesting. Neither Intel or AMD has given much thought to putting cores of different sizes and performance/efficiency on the same die. That's the big.LITTLE/DynamIQ approach that is found in hundreds of millions of smartphone chips. It will be interesting to see if these kinds of designs benefit laptop and tablet users. Also, my understanding is that Intel could mix cores from different process nodes. So they could put one big "10nm" core alongside several "14nm+++++" cores.

      This 3D packaging approach they are experimenting with is interesting but is far from what may be available in a decade or two, where 3D placement of layers of cores and memory could allow computers to be thousands of times faster [darpa.mil].

      If you're interested in AMD, then you should be looking at this leak* [wccftech.com] and keeping your eyes peeled on CES 2019. AMD is likely to increase "7nm" Ryzen core counts up to 16, from 8. That's right, Ryzen with 16 cores, not just Threadripper. Combine that with about a 20-25% performance increase from IPC improvements and clock speeds, and you can see why Intel is getting antsy and showing off its goods.

      Apparently this new info about "12nm" mobile APUs [wccftech.com] just came out. I'm not going to touch it since I want to see them double core counts to 8, from 4, which they might do on the "7nm" node in 2020. And I still want AV1 support [wikipedia.org] in any new hardware.

      *The YouTuber who released the leak has walked back some details, such as AMD's use of "14nm" I/O dies to connect 8-core chiplets shown in the diagrams. That was a guess on his part, and his sources say that it will just use Infinity Fabric.
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  • (Score: 2) by takyon on Friday December 14 2018, @07:02AM

    by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday December 14 2018, @07:02AM (#774308) Journal
  • (Score: 2) by Pino P on Friday December 14 2018, @02:09PM

    by Pino P (4721) on Friday December 14 2018, @02:09PM (#774391) Journal

    I saw "Xe" with the 'e' smaller than the 'X', and my next thought was of Blackwater Security, a private military and law enforcement training company that changed its name to "Xe Services" [wikipedia.org] in 2009 and then reestablished as "Academi" a year later.

  • (Score: 1) by EEMac on Friday December 14 2018, @04:41PM (1 child)

    by EEMac (6423) on Friday December 14 2018, @04:41PM (#774458)

    Does Intel really have any credibility left for preannouncements?

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