from the like-pancakes dept.
JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of an update to JESD235 High Bandwidth Memory (HBM) DRAM standard.
[...] JEDEC standard JESD235B for HBM leverages Wide I/O and TSV technologies to support densities up to 24 GB per device at speeds up to 307 GB/s. This bandwidth is delivered across a 1024-bit wide device interface that is divided into 8 independent channels on each DRAM stack. The standard can support 2-high, 4-high, 8-high, and 12-high TSV stacks of DRAM at full bandwidth to allow systems flexibility on capacity requirements from 1 GB – 24 GB per stack.
This update extends the per pin bandwidth to 2.4 Gbps, adds a new footprint option to accommodate the 16 Gb-layer and 12-high configurations for higher density components, and updates the MISR polynomial options for these new configurations.
Some existing High Bandwidth Memory products already had a per pin bandwidth of 2.4 Gbps. However, the increase in stack size and density could allow a product with 96 GB of DRAM using just four stacks (16 Gb DRAM × 12 × 4), up from 32 GB (8 Gb DRAM × 8 × 4).
In response to increased demand, Samsung is increasing production of the densest HBM2 DRAM available:
Samsung on Tuesday announced that it is increasing production volumes of its 8 GB, 8-Hi HBM2 DRAM stacks due to growing demand. In the coming months the company's 8 GB HBM2 chips will be used for several applications, including those for consumers, professionals, AI, as well as for parallel computing. Meanwhile, AMD's Radeon Vega graphics cards for professionals and gamers will likely be the largest consumers of HBM2 in terms of volume. And while AMD is traditionally a SK Hynix customer, the timing of this announcement with AMD's launches certainly suggests that AMD is likely a Samsung customer this round as well.
Samsung's 8 GB HBM Gen 2 memory KGSDs (known good stacked die) are based on eight 8-Gb DRAM devices in an 8-Hi stack configuration. The memory components are interconnected using TSVs and feature over 5,000 TSV interconnects each. Every KGSD has a 1024-bit bus and offers up to 2 Gbps data rate per pin, thus providing up to 256 GB/s of memory bandwidth per single 8-Hi stack. The company did not disclose power consumption and heat dissipation of its HBM memory components, but we have reached out [to] Samsung for additional details.
Samsung has introduced the industry's first memory that correspond to the HBM2E specification. The company's new Flashbolt memory stacks increase performance by 33% and offer double per-die as well as double per-package capacity. Samsung introduced its HBM2E DRAMs at GTC, indicating that the gaming market is a target market for this memory.
Samsung's Flashbolt KGSDs (known good stacked die) are based on eight 16-Gb memory dies interconnected using TSVs (through silicon vias) in an 8-Hi stack configuration. Every Flashbolt package features a 1024-bit bus with a 3.2 Gbps data transfer speed per pin, thus offering up to 410 GB/s of bandwidth per KGSD.
Samsung positions its Flashbolt KGSDs for next-gen datacenter, HPC, AI/ML, and graphics applications. By using four Flashbolt stacks with a processor featuring a 4096-bit memory interface, developers can get 64 GB of memory with a 1.64 TB/s peak bandwidth, something that will be a great advantage for capacity and bandwidth-hungry chips. With two KGSDs they get 32 GB of DRAM with an 820 GB/s peak bandwidth.
Also at Tom's Hardware.
[HBM is High Bandwidth Memory. -Ed.]
SK Hynix this morning has thrown their hat into the ring as the second company to announce memory based on the HBM2E standard. While the company isn't using any kind of flash name for the memory (ala Samsung's Flashbolt), the idea is the same: releasing faster and higher density HBM2 memory for the next generation of high-end processors. Hynix's HBM2E memory will reach up to 3.6 Gbps, which as things currently stand, will make it the fastest HBM2E memory on the market when it ships in 2020.
As a quick refresher, HBM2E is a small update to the HBM2 standard to improve its performance, serving as a mid-generational kicker of sorts to allow for higher clockspeeds, higher densities (up to 24GB with 12 layers), and the underlying changes that are required to make those happen. Samsung was the first memory vendor to announce HBM2E memory earlier this year, with their 16GB/stack Flashbolt memory, which runs at up to 3.2 Gbps. At the time, Samsung did not announce a release date, and to the best of our knowledge, mass production still hasn't begun.
[...] [SK Hynix's] capacity is doubling, from 8 Gb/layer to 16 Gb/layer, allowing a full 8-Hi stack to reach a total of 16GB. It's worth noting that the revised HBM2 standard actually allows for 12-Hi stacks, for a total of 24GB/stack, however we've yet to see anyone announce memory quite that dense.
See also: HBM2E: The E Stands For Evolutionary
Samsung has developed the first 12-layer High Bandwidth Memory stacks:
Samsung's 12-layer DRAM KGSDs (known good stack die) will feature 60,000 [through silicon via (TSV)] holes which is why the manufacturer considers its technology one of the most challenging packaging for mass production. Despite increase of the number of layers from eight to 12, thickness of the package will remain at 720 microns, so Samsung's partners will not have to change anything on their side to use the new technology. It does mean that we're seeing DRAM layers getting thinner, with acceptable yields for high-end products.
One of the first products to use Samsung's 12-layer DRAM packaging technology will be the company's 24 GB HBM2 KGSDs that will be mass produced shortly. These devices will allow developers of CPUs, GPUs, and FPGAs to install 48 GB or 96 GB of memory in case of 2048 or 4096-bit buses, respectively. It also allows for 12 GB and 6 GB stacks with less dense configurations.
"12-Hi" stacks were added to the HBM2 standard back in December, but there were no immediate plans by Samsung or SK Hynix to manufacture it.
Future AMD CPUs (particularly Epyc) may feature HBM stacks somewhere on the CPU die. Intel has already used its embedded multi-die interconnect bridge (EMIB) technology with HBM to create an advanced APU with AMD's own graphics, and is using HBM on field programmable gate arrays (FPGAs) and other products.
AMD's Radeon VII GPU has 16 GB of HBM2. Nvidia's V100 GPU has 16 or 32 GB on a 4,096-bit memory bus.
Also at Electronics Weekly.
SK Hynix has licensed technology that could enable the production of 16-layer High Bandwidth Memory (HBM) stacks. Bandwidth could also be increased by a superior interconnect density:
SK Hynix has inked a new broad patent and technology licensing agreement with Xperi Corp. Among other things, the company licensed the DBI Ultra 2.5D/3D interconnect technology developed by Invensas. The latter was designed to enable building up to 16-Hi chip assemblies, including next-generation memory, and highly-integrated SoCs that feature numerous homogeneous layers.
Invensas' DBI Ultra is a proprietary die-to-wafer hybrid bonding interconnect technology that supports from 100,000 to 1,000,000 interconnects per mm2, using interconnect pitches as small as 1 µm. According to the company, the much greater number of interconnects can offer dramatically increased bandwidth vs. conventional copper pillar interconnect technology, which only goes as high as 625 interconnects per mm2. The small interconnects also offer a shorter z-height, making it possible to build a stacked chip with 16 layers in the same space as conventional 8-Hi chips, allowing for greater memory densities.
JEDEC (Joint Electron Device Engineering Council) has updated the HBM2 standard to accommodate 3.2Gbps/pin speeds. This is in line with Samsung's "Flashbolt" HBM2E memory (although SK Hynix and Samsung may push speeds to a further 3.6Gbps or 4.2Gbps/pin), which will enter into mass production soon. JEDEC has not adopted the "HBM2E" nomenclature used by Samsung, SK Hynix, and others.